; ; Pole_Zero_Filter_Phase from 0x105df8 to 0x105eb8 (192 bytes) ; ; 5 xrefs: ; > Pole_Zero_Filter @ 0x105df4 ; > .Pole_Zero_Filter_Phase @ 0x109e6c ; > @ 0x59e0 ; > .Pole_Zero_Filter_Phase @ 0x109e64 ; > @ 0x1117f8 ; ; This function is hookable on this platform! ; ; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA ; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings ; STP X29, X30, [SP,#-0x10+var_s0]! ; +0x0, 0x105df8 SXTH W6, W6 ; +0x4, 0x105dfc SXTH X1, W1 ; +0x8, 0x105e00 MOV X29, SP ; +0xc, 0x105e04 SXTH X3, W3 ; +0x10, 0x105e08 AND W7, W6, #1 ; +0x14, 0x105e0c LDR S0, [X5] ; +0x18, 0x105e10 LDR S5, [X5,#4] ; +0x1c, 0x105e14 LDR S4, [X4] ; +0x20, 0x105e18 LDR S6, [X4,#4] ; +0x24, 0x105e1c TBNZ W6, #0, loc_105E94 ; +0x28, 0x105e20 FMOV S2, S5 ; +0x2c, 0x105e24 CBZ W6, loc_105E80 ; +0x30, 0x105e28 FNEG S4, S4 ; +0x34, 0x105e2c MOV W4, W7 ; +0x38, 0x105e30 LSL X8, X1, #2 ; +0x3c, 0x105e34 LSL X7, X3, #2 ; +0x40, 0x105e38 LSL X1, X1, #3 ; +0x44, 0x105e3c LSL X3, X3, #3 ; +0x48, 0x105e40 LDR S1, [X0] ; +0x4c, 0x105e44 ADD W4, W4, #2 ; +0x50, 0x105e48 LDR S2, [X0,X8] ; +0x54, 0x105e4c CMP W4, W6 ; +0x58, 0x105e50 FMUL S3, S1, S6 ; +0x5c, 0x105e54 ADD X0, X0, X1 ; +0x60, 0x105e58 FMADD S1, S2, S6, S1 ; +0x64, 0x105e5c FMADD S0, S0, S4, S3 ; +0x68, 0x105e60 FADD S3, S0, S5 ; +0x6c, 0x105e64 FMOV S5, S2 ; +0x70, 0x105e68 FMADD S0, S3, S4, S1 ; +0x74, 0x105e6c STR S3, [X2] ; +0x78, 0x105e70 STR S0, [X2,X7] ; +0x7c, 0x105e74 ADD X2, X2, X3 ; +0x80, 0x105e78 B.CC loc_105E44 ; +0x84, 0x105e7c MOV W0, #0 ; +0x88, 0x105e80 STR S0, [X5] ; +0x8c, 0x105e84 STR S2, [X5,#4] ; +0x90, 0x105e88 LDP X29, X30, [SP+var_s0],#0x10 ; +0x94, 0x105e8c RET ; +0x98, 0x105e90 ADRP X2, #aPoleZeroFilter_1@PAGE; "Pole_Zero_Filter" ; +0x9c, 0x105e94 ADRP X0, #aSrcPl2EncodeSu@PAGE; "../../src/pl2_encode_subroutine.c" ; +0xa0, 0x105e98 ADD X2, X2, #aPoleZeroFilter_1@PAGEOFF; "Pole_Zero_Filter" ; +0xa4, 0x105e9c ADRP X3, #a0Dspsblocksize@PAGE; "0 == dspsBlockSize % 2" ; +0xa8, 0x105ea0 ADD X0, X0, #aSrcPl2EncodeSu@PAGEOFF; "../../src/pl2_encode_subroutine.c" ; +0xac, 0x105ea4 MOV W1, #0x6F6 ; +0xb0, 0x105ea8 ADD X2, X2, #0x20 ; ' ' ; +0xb4, 0x105eac ADD X3, X3, #a0Dspsblocksize@PAGEOFF; "0 == dspsBlockSize % 2" ; +0xb8, 0x105eb0 BL .__assert2 ; +0xbc, 0x105eb4