{"type": "func", "start": 1052864, "end": 1055384, "name": "sub_1010C0", "pseudocode": "// \n// sub_1010C0 from 0x1010c0 to 0x101a98 (2520 bytes)\n// \n// 1 xrefs:\n// > sub_101080 @ 0x1010a4\n// \n// This function is hookable on this platform!\n// \n// Using BromaIDA 8.0.0 @ https://github.com/Stazzical/BromaIDA\n// Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings\n// \n\nint8x16_t *__usercall sub_1010C0@(\n int8x16_t *result@,\n int8x16_t *a2@,\n int a3@,\n float32x4_t *a4@,\n int a5@,\n int a6@,\n int a7@,\n int8x16_t a8@)\n{\n int v8; // w9\n int8x16_t v9; // q0\n int v10; // w10\n int8x16_t v11; // q1\n int v12; // w11\n __int64 v13; // x14\n int8x16_t *v14; // x16\n float32x4_t *v15; // x17\n int v16; // w4\n int8x16_t v17; // q2\n int8x16_t v18; // q4\n int8x16_t v19; // q5\n int8x16_t v20; // q6\n int8x16_t v21; // q7\n int32x4_t v22; // q16\n int32x4_t v23; // q5\n int v24; // w4\n float32x4_t v25; // t1\n float32x4_t v26; // q3\n float32x4_t v27; // q2\n int8x16_t *v28; // x16\n float32x4_t *v29; // x17\n int v30; // w4\n int8x16_t v31; // q3\n int8x16_t v32; // q5\n int8x16_t v33; // q7\n int8x16_t v34; // q17\n int8x16_t v35; // q19\n int32x4_t v36; // q6\n int32x4_t v37; // q16\n int v38; // w4\n float32x4_t v39; // q4\n float32x4_t v40; // q5\n float32x4_t v41; // q4\n float32x4_t v42; // q3\n float32x4_t v43; // q2\n int8x16_t *v44; // x16\n float32x4_t *v45; // x17\n int8x16_t v46; // q4\n int v47; // w4\n int8x16_t v48; // q6\n int8x16_t v49; // q16\n int8x16_t v50; // q18\n int8x16_t v51; // q20\n int32x4_t v52; // q7\n int32x4_t v53; // q17\n int v54; // w4\n float32x4_t v55; // q5\n float32x4_t v56; // q2\n float32x4_t v57; // q3\n float32x4_t v58; // q4\n int8x16_t *v59; // x16\n float32x4_t *v60; // x17\n int8x16_t v61; // q5\n int v62; // w4\n float32x4_t v63; // q21\n int8x16_t v64; // q7\n int8x16_t v65; // q17\n float32x4_t v66; // q16\n float32x4_t v67; // q18\n int8x16_t v68; // q19\n int8x16_t v69; // q21\n int32x4_t v70; // q16\n int32x4_t v71; // q18\n int v72; // w4\n float32x4_t v73; // q6\n float32x4_t v74; // q7\n float32x4_t v75; // q16\n float32x4_t v76; // q6\n float32x4_t v77; // q5\n float32x4_t v78; // q2\n float32x4_t v79; // q3\n float32x4_t v80; // q4\n int8x16_t *v81; // x16\n int8x16_t v82; // q6\n float32x4_t *v83; // x17\n int v84; // w4\n int8x16_t v85; // q16\n int8x16_t v86; // q7\n int8x16_t v87; // q19\n int8x16_t v88; // q21\n int32x4_t v89; // q17\n int32x4_t v90; // q20\n int v91; // w4\n float32x4_t v92; // q17\n float32x4_t v93; // q7\n float32x4_t v94; // q7\n float32x4_t v95; // q4\n float32x4_t v96; // q2\n float32x4_t v97; // q3\n float32x4_t v98; // q5\n float32x4_t v99; // q6\n int8x16_t *v100; // x16\n int8x16_t v101; // q7\n float32x4_t *v102; // x17\n int v103; // w4\n int8x16_t v104; // q18\n int8x16_t v105; // q17\n int8x16_t v106; // q19\n int32x4_t v107; // q21\n int8x16_t v108; // q20\n int32x4_t v109; // q22\n int v110; // w4\n float32x4_t v111; // q16\n float32x4_t v112; // q17\n float32x4_t v113; // q18\n float32x4_t v114; // q16\n float32x4_t v115; // q7\n float32x4_t v116; // q2\n float32x4_t v117; // q3\n float32x4_t v118; // q4\n float32x4_t v119; // q5\n float32x4_t v120; // q6\n int8x16_t v121; // q16\n int8x16_t *v122; // x16\n float32x4_t *v123; // x17\n int v124; // w4\n int8x16_t v125; // q18\n int8x16_t v126; // q17\n int8x16_t v127; // q19\n int8x16_t v128; // q20\n int32x4_t v129; // q21\n int32x4_t v130; // q22\n int v131; // w4\n float32x4_t v132; // q18\n float32x4_t v133; // q17\n float32x4_t v134; // q17\n float32x4_t v135; // q6\n float32x4_t v136; // q2\n float32x4_t v137; // q3\n float32x4_t v138; // q4\n float32x4_t v139; // q5\n float32x4_t v140; // q7\n float32x4_t v141; // q16\n int8x16_t v142; // q17\n int8x16_t *v143; // x16\n float32x4_t *v144; // x17\n int v145; // w4\n float32x4_t v146; // q22\n int8x16_t v147; // q20\n int8x16_t v148; // q19\n int32x4_t v149; // q23\n float32x4_t v150; // q24\n float32x4_t v151; // q27\n int8x16_t v152; // q21\n int8x16_t v153; // q22\n int32x4_t v154; // q24\n int v155; // w4\n float32x4_t v156; // q18\n float32x4_t v157; // q19\n float32x4_t v158; // q20\n float32x4_t v159; // q18\n\n v9.n128_u64[1] = -1;\n v9.n128_u64[0] = -1;\n v10 = 0;\n v11 = vmvnq_s8(a8);\n v12 = a6 >> 2;\n v13 = a5;\n while ( v10 < a3 )\n {\n switch ( a7 )\n {\n case 0:\n case 1:\n case 2:\n case 3:\n v14 = a2;\n v15 = a4;\n v16 = a6 >> 2;\n v17 = vandq_s8(*result, v9);\n if ( v12 )\n {\n do\n {\n v18 = vmulq_f32(*v15, v17);\n v19 = vmulq_f32(v15[8], v17);\n v20 = vmulq_f32(v15[16], v17);\n v21 = vmulq_f32(v15[24], v17);\n v22 = vextq_s8(v18, vextq_s8(v19, v18, 8u), 8u);\n v18.n128_u64[1] = v19.n128_u64[0];\n v23 = vextq_s8(v20, vextq_s8(v21, v20, 8u), 8u);\n v20.n128_u64[1] = v21.n128_u64[0];\n --v16;\n *v14 = vaddq_f32(\n vuzp1q_s32(v18, v20),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v14, v11), vuzp2q_s32(v18, v20)), vuzp1q_s32(v22, v23)),\n vuzp2q_s32(v22, v23)));\n ++v14;\n v15 += 32;\n }\n while ( v16 );\n }\n v24 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n v25 = *v15;\n v15 += 8;\n --v24;\n v26 = vmulq_f32(v25, v17);\n v14->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v26, v26).n128_u64[0])\n + COERCE_FLOAT(v14->n128_u32[0] & v8);\n v14 = (int8x16_t *)((char *)v14 + 4);\n }\n while ( v24 );\n }\n goto LABEL_43;\n case 4:\n case 5:\n case 6:\n case 7:\n v27 = *result;\n v28 = a2;\n v29 = a4;\n v30 = a6 >> 2;\n v31 = vandq_s8(result[1], v9);\n if ( v12 )\n {\n do\n {\n v32 = vmlaq_f32(vmulq_f32(*v29, v27), v31, v29[1]);\n v33 = vmlaq_f32(vmulq_f32(v29[8], v27), v31, v29[9]);\n v34 = vmlaq_f32(vmulq_f32(v29[16], v27), v31, v29[17]);\n v35 = vmlaq_f32(vmulq_f32(v29[24], v27), v31, v29[25]);\n v36 = vextq_s8(v32, vextq_s8(v33, v32, 8u), 8u);\n v37 = vextq_s8(v34, vextq_s8(v35, v34, 8u), 8u);\n v32.n128_u64[1] = v33.n128_u64[0];\n v34.n128_u64[1] = v35.n128_u64[0];\n --v30;\n *v28 = vaddq_f32(\n vuzp1q_s32(v32, v34),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v28, v11), vuzp2q_s32(v32, v34)), vuzp1q_s32(v36, v37)),\n vuzp2q_s32(v36, v37)));\n ++v28;\n v29 += 32;\n }\n while ( v30 );\n }\n v38 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n v39 = *v29;\n v40 = v29[1];\n v29 += 8;\n --v38;\n v41 = vmlaq_f32(vmulq_f32(v39, v27), v31, v40);\n v28->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v41, v41).n128_u64[0])\n + COERCE_FLOAT(v28->n128_u32[0] & v8);\n v28 = (int8x16_t *)((char *)v28 + 4);\n }\n while ( v38 );\n }\n goto LABEL_43;\n case 8:\n case 9:\n case 10:\n case 11:\n v42 = result[1];\n v43 = *result;\n v44 = a2;\n v45 = a4;\n v46 = vandq_s8(result[2], v9);\n v47 = a6 >> 2;\n if ( v12 )\n {\n do\n {\n v48 = vmlaq_f32(vmlaq_f32(vmulq_f32(*v45, v43), v42, v45[1]), v46, v45[2]);\n v49 = vmlaq_f32(vmlaq_f32(vmulq_f32(v45[8], v43), v42, v45[9]), v46, v45[10]);\n v50 = vmlaq_f32(vmlaq_f32(vmulq_f32(v45[16], v43), v42, v45[17]), v46, v45[18]);\n v51 = vmlaq_f32(vmlaq_f32(vmulq_f32(v45[24], v43), v42, v45[25]), v46, v45[26]);\n v52 = vextq_s8(v48, vextq_s8(v49, v48, 8u), 8u);\n v53 = vextq_s8(v50, vextq_s8(v51, v50, 8u), 8u);\n v48.n128_u64[1] = v49.n128_u64[0];\n v50.n128_u64[1] = v51.n128_u64[0];\n --v47;\n *v44 = vaddq_f32(\n vuzp1q_s32(v48, v50),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v44, v11), vuzp2q_s32(v48, v50)), vuzp1q_s32(v52, v53)),\n vuzp2q_s32(v52, v53)));\n ++v44;\n v45 += 32;\n }\n while ( v47 );\n }\n v54 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n --v54;\n v55 = vmlaq_f32(vmlaq_f32(vmulq_f32(*v45, v43), v42, v45[1]), v46, v45[2]);\n v44->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v55, v55).n128_u64[0])\n + COERCE_FLOAT(v44->n128_u32[0] & v8);\n v44 = (int8x16_t *)((char *)v44 + 4);\n v45 += 8;\n }\n while ( v54 );\n }\n goto LABEL_43;\n case 12:\n case 13:\n case 14:\n case 15:\n v56 = result[2];\n v57 = *result;\n v58 = result[1];\n v59 = a2;\n v60 = a4;\n v61 = vandq_s8(result[3], v9);\n v62 = a6 >> 2;\n if ( v12 )\n {\n do\n {\n v63 = vmlaq_f32(vmulq_f32(v60[24], v57), v58, v60[25]);\n v64 = vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(*v60, v57), v58, v60[1]), v56, v60[2]), v61, v60[3]);\n v65 = vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(v60[8], v57), v58, v60[9]), v56, v60[10]), v61, v60[11]);\n --v62;\n v67 = v60[26];\n v66 = v60[27];\n v68 = vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(v60[16], v57), v58, v60[17]), v56, v60[18]), v61, v60[19]);\n v60 += 32;\n v69 = vmlaq_f32(vmlaq_f32(v63, v56, v67), v61, v66);\n v70 = vextq_s8(v64, vextq_s8(v65, v64, 8u), 8u);\n v71 = vextq_s8(v68, vextq_s8(v69, v68, 8u), 8u);\n v64.n128_u64[1] = v65.n128_u64[0];\n v68.n128_u64[1] = v69.n128_u64[0];\n *v59 = vaddq_f32(\n vuzp1q_s32(v64, v68),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v59, v11), vuzp2q_s32(v64, v68)), vuzp1q_s32(v70, v71)),\n vuzp2q_s32(v70, v71)));\n ++v59;\n }\n while ( v62 );\n }\n v72 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n --v72;\n v73 = vmlaq_f32(vmulq_f32(*v60, v57), v58, v60[1]);\n v75 = v60[2];\n v74 = v60[3];\n v60 += 8;\n v76 = vmlaq_f32(vmlaq_f32(v73, v56, v75), v61, v74);\n v59->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v76, v76).n128_u64[0])\n + COERCE_FLOAT(v59->n128_u32[0] & v8);\n v59 = (int8x16_t *)((char *)v59 + 4);\n }\n while ( v72 );\n }\n goto LABEL_43;\n case 16:\n case 17:\n case 18:\n case 19:\n v77 = result[3];\n v78 = *result;\n v79 = result[1];\n v80 = result[2];\n v81 = a2;\n v82 = vandq_s8(result[4], v9);\n v83 = a4;\n v84 = a6 >> 2;\n if ( v12 )\n {\n do\n {\n --v84;\n v85 = vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(*v83, v78), v79, v83[1]), v80, v83[2]), v77, v83[3]),\n v82,\n v83[4]);\n v86 = vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(v83[8], v78), v79, v83[9]), v80, v83[10]), v77, v83[11]),\n v82,\n v83[12]);\n v87 = vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(v83[16], v78), v79, v83[17]), v80, v83[18]), v77, v83[19]),\n v82,\n v83[20]);\n v88 = vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(v83[24], v78), v79, v83[25]), v80, v83[26]), v77, v83[27]),\n v82,\n v83[28]);\n v89 = vextq_s8(v85, vextq_s8(v86, v85, 8u), 8u);\n v90 = vextq_s8(v87, vextq_s8(v88, v87, 8u), 8u);\n v85.n128_u64[1] = v86.n128_u64[0];\n v87.n128_u64[1] = v88.n128_u64[0];\n *v81 = vaddq_f32(\n vuzp1q_s32(v85, v87),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v81, v11), vuzp2q_s32(v85, v87)), vuzp1q_s32(v89, v90)),\n vuzp2q_s32(v89, v90)));\n ++v81;\n v83 += 32;\n }\n while ( v84 );\n }\n v91 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n --v91;\n v92 = v83[4];\n v93 = vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(*v83, v78), v79, v83[1]), v80, v83[2]), v77, v83[3]);\n v83 += 8;\n v94 = vmlaq_f32(v93, v82, v92);\n v81->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v94, v94).n128_u64[0])\n + COERCE_FLOAT(v81->n128_u32[0] & v8);\n v81 = (int8x16_t *)((char *)v81 + 4);\n }\n while ( v91 );\n }\n goto LABEL_43;\n case 20:\n case 21:\n case 22:\n case 23:\n v95 = result[4];\n v96 = *result;\n v97 = result[1];\n v98 = result[2];\n v99 = result[3];\n v100 = a2;\n v101 = vandq_s8(result[5], v9);\n v102 = a4;\n v103 = a6 >> 2;\n if ( v12 )\n {\n do\n {\n v104 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(*v102, v96), v97, v102[1]), v98, v102[2]), v99, v102[3]),\n v95,\n v102[4]),\n v101,\n v102[5]);\n --v103;\n v105 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v102[8], v96), v97, v102[9]), v98, v102[10]),\n v99,\n v102[11]),\n v95,\n v102[12]),\n v101,\n v102[13]);\n v106 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v102[16], v96), v97, v102[17]), v98, v102[18]),\n v99,\n v102[19]),\n v95,\n v102[20]),\n v101,\n v102[21]);\n v107 = vextq_s8(v104, vextq_s8(v105, v104, 8u), 8u);\n v108 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v102[24], v96), v97, v102[25]), v98, v102[26]),\n v99,\n v102[27]),\n v95,\n v102[28]),\n v101,\n v102[29]);\n v109 = vextq_s8(v106, vextq_s8(v108, v106, 8u), 8u);\n v104.n128_u64[1] = v105.n128_u64[0];\n v106.n128_u64[1] = v108.n128_u64[0];\n *v100 = vaddq_f32(\n vuzp1q_s32(v104, v106),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v100, v11), vuzp2q_s32(v104, v106)), vuzp1q_s32(v107, v109)),\n vuzp2q_s32(v107, v109)));\n ++v100;\n v102 += 32;\n }\n while ( v103 );\n }\n v110 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n --v110;\n v111 = vmlaq_f32(vmlaq_f32(vmlaq_f32(vmulq_f32(*v102, v96), v97, v102[1]), v98, v102[2]), v99, v102[3]);\n v113 = v102[4];\n v112 = v102[5];\n v102 += 8;\n v114 = vmlaq_f32(vmlaq_f32(v111, v95, v113), v101, v112);\n v100->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v114, v114).n128_u64[0])\n + COERCE_FLOAT(v100->n128_u32[0] & v8);\n v100 = (int8x16_t *)((char *)v100 + 4);\n }\n while ( v110 );\n }\n goto LABEL_43;\n case 24:\n case 25:\n case 26:\n case 27:\n v115 = result[5];\n v116 = *result;\n v117 = result[1];\n v118 = result[2];\n v119 = result[3];\n v120 = result[4];\n v121 = vandq_s8(result[6], v9);\n v122 = a2;\n v123 = a4;\n v124 = a6 >> 2;\n if ( v12 )\n {\n do\n {\n --v124;\n v125 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(*v123, v116), v117, v123[1]), v118, v123[2]),\n v119,\n v123[3]),\n v120,\n v123[4]),\n v115,\n v123[5]),\n v121,\n v123[6]);\n v126 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v123[8], v116), v117, v123[9]), v118, v123[10]),\n v119,\n v123[11]),\n v120,\n v123[12]),\n v115,\n v123[13]),\n v121,\n v123[14]);\n v127 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v123[16], v116), v117, v123[17]), v118, v123[18]),\n v119,\n v123[19]),\n v120,\n v123[20]),\n v115,\n v123[21]),\n v121,\n v123[22]);\n v128 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v123[24], v116), v117, v123[25]), v118, v123[26]),\n v119,\n v123[27]),\n v120,\n v123[28]),\n v115,\n v123[29]),\n v121,\n v123[30]);\n v129 = vextq_s8(v125, vextq_s8(v126, v125, 8u), 8u);\n v130 = vextq_s8(v127, vextq_s8(v128, v127, 8u), 8u);\n v125.n128_u64[1] = v126.n128_u64[0];\n v127.n128_u64[1] = v128.n128_u64[0];\n *v122 = vaddq_f32(\n vuzp1q_s32(v125, v127),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v122, v11), vuzp2q_s32(v125, v127)), vuzp1q_s32(v129, v130)),\n vuzp2q_s32(v129, v130)));\n ++v122;\n v123 += 32;\n }\n while ( v124 );\n }\n v131 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n --v131;\n v132 = v123[6];\n v133 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(*v123, v116), v117, v123[1]), v118, v123[2]),\n v119,\n v123[3]),\n v120,\n v123[4]),\n v115,\n v123[5]);\n v123 += 8;\n v134 = vmlaq_f32(v133, v121, v132);\n v122->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v134, v134).n128_u64[0])\n + COERCE_FLOAT(v122->n128_u32[0] & v8);\n v122 = (int8x16_t *)((char *)v122 + 4);\n }\n while ( v131 );\n }\n goto LABEL_43;\n case 28:\n case 29:\n case 30:\n case 31:\n v135 = result[6];\n v136 = *result;\n v137 = result[1];\n v138 = result[2];\n v139 = result[3];\n v140 = result[4];\n v141 = result[5];\n v142 = vandq_s8(result[7], v9);\n v143 = a2;\n v144 = a4;\n v145 = a6 >> 2;\n if ( v12 )\n {\n do\n {\n --v145;\n v146 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v144[24], v136), v137, v144[25]), v138, v144[26]),\n v139,\n v144[27]),\n v140,\n v144[28]),\n v141,\n v144[29]);\n v147 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(*v144, v136), v137, v144[1]), v138, v144[2]),\n v139,\n v144[3]),\n v140,\n v144[4]),\n v141,\n v144[5]),\n v135,\n v144[6]),\n v142,\n v144[7]);\n v148 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v144[8], v136), v137, v144[9]), v138, v144[10]),\n v139,\n v144[11]),\n v140,\n v144[12]),\n v141,\n v144[13]),\n v135,\n v144[14]),\n v142,\n v144[15]);\n v149 = vextq_s8(v147, vextq_s8(v148, v147, 8u), 8u);\n v150 = v144[30];\n v151 = v144[31];\n v152 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(v144[16], v136), v137, v144[17]), v138, v144[18]),\n v139,\n v144[19]),\n v140,\n v144[20]),\n v141,\n v144[21]),\n v135,\n v144[22]),\n v142,\n v144[23]);\n v147.n128_u64[1] = v148.n128_u64[0];\n v144 += 32;\n v153 = vmlaq_f32(vmlaq_f32(v146, v135, v150), v142, v151);\n v154 = vextq_s8(v152, vextq_s8(v153, v152, 8u), 8u);\n v152.n128_u64[1] = v153.n128_u64[0];\n *v143 = vaddq_f32(\n vuzp1q_s32(v147, v152),\n vaddq_f32(\n vaddq_f32(vaddq_f32(vandq_s8(*v143, v11), vuzp2q_s32(v147, v152)), vuzp1q_s32(v149, v154)),\n vuzp2q_s32(v149, v154)));\n ++v143;\n }\n while ( v145 );\n }\n v155 = a6 & 3;\n if ( (a6 & 3) != 0 )\n {\n do\n {\n --v155;\n v156 = vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(\n vmlaq_f32(vmlaq_f32(vmulq_f32(*v144, v136), v137, v144[1]), v138, v144[2]),\n v139,\n v144[3]),\n v140,\n v144[4]),\n v141,\n v144[5]);\n v157 = v144[6];\n v158 = v144[7];\n v144 += 8;\n v159 = vmlaq_f32(vmlaq_f32(v156, v135, v157), v142, v158);\n v143->n128_f32[0] = vaddv_f32((float32x2_t)vpaddq_f32(v159, v159).n128_u64[0])\n + COERCE_FLOAT(v143->n128_u32[0] & v8);\n v143 = (int8x16_t *)((char *)v143 + 4);\n }\n while ( v155 );\n }\nLABEL_43:\n a2 = (int8x16_t *)((char *)a2 + 4 * a6);\n break;\n default:\n break;\n }\n result = (int8x16_t *)((char *)result + 4 * v13);\n ++v10;\n }\n return result;\n}", "assembly": "; \n; sub_1010C0 from 0x1010c0 to 0x101a98 (2520 bytes)\n; \n; 1 xrefs:\n; > sub_101080 @ 0x1010a4\n; \n; This function is hookable on this platform!\n; \n; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA\n; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings\n; \n\nADRP X10, #xmmword_2F650@PAGE ; +0x0, 0x1010c0\nLDR Q0, [X10,#xmmword_2F650@PAGEOFF] ; +0x4, 0x1010c4\nMOV W10, #0xFFFFFFFF ; +0x8, 0x1010c8\nINS V0.S[2], W10 ; +0xc, 0x1010cc\nMOV W10, #0xFFFFFFFF ; +0x10, 0x1010d0\nINS V0.S[1], W10 ; +0x14, 0x1010d4\nMOV W15, #0xFFFFFFFF ; +0x18, 0x1010d8\nINS V0.S[0], W15 ; +0x1c, 0x1010dc\nADRP X15, #jpt_10111C@PAGE ; +0x20, 0x1010e0\nMOV W10, WZR ; +0x24, 0x1010e4\nMVN V1.16B, V1.16B ; +0x28, 0x1010e8\nASR W11, W5, #2 ; +0x2c, 0x1010ec\nAND W12, W5, #3 ; +0x30, 0x1010f0\nSXTW X13, W5 ; +0x34, 0x1010f4\nSXTW X14, W4 ; +0x38, 0x1010f8\nADD X15, X15, #jpt_10111C@PAGEOFF ; +0x3c, 0x1010fc\nCMP W10, W2 ; +0x40, 0x101100\nB.GE locret_101A94 ; +0x44, 0x101104\nCMP W8, #0x1F; switch 32 cases ; +0x48, 0x101108\nB.HI def_10111C; jumptable 000000000010111C default case ; +0x4c, 0x10110c\nADR X16, loc_101120; jumptable 000000000010111C cases 0-3 ; +0x50, 0x101110\nLDRH W17, [X15,X8,LSL#1] ; +0x54, 0x101114\nADD X16, X16, X17,LSL#2 ; +0x58, 0x101118\nBR X16; switch jump ; +0x5c, 0x10111c\nLDR Q2, [X0]; jumptable 000000000010111C cases 0-3 ; +0x60, 0x101120\nMOV X16, X1 ; +0x64, 0x101124\nMOV X17, X3 ; +0x68, 0x101128\nMOV W4, W11 ; +0x6c, 0x10112c\nAND V2.16B, V2.16B, V0.16B ; +0x70, 0x101130\nCBZ W4, loc_1011A8 ; +0x74, 0x101134\nLDR Q4, [X17] ; +0x78, 0x101138\nLDR Q5, [X17,#0x80] ; +0x7c, 0x10113c\nLDR Q6, [X17,#0x100] ; +0x80, 0x101140\nLDR Q7, [X17,#0x180] ; +0x84, 0x101144\nLDR Q3, [X16] ; +0x88, 0x101148\nFMUL V4.4S, V4.4S, V2.4S ; +0x8c, 0x10114c\nFMUL V5.4S, V5.4S, V2.4S ; +0x90, 0x101150\nFMUL V6.4S, V6.4S, V2.4S ; +0x94, 0x101154\nFMUL V7.4S, V7.4S, V2.4S ; +0x98, 0x101158\nEXT V16.16B, V5.16B, V4.16B, #8 ; +0x9c, 0x10115c\nEXT V16.16B, V4.16B, V16.16B, #8 ; +0xa0, 0x101160\nINS V4.D[1], V5.D[0] ; +0xa4, 0x101164\nEXT V5.16B, V7.16B, V6.16B, #8 ; +0xa8, 0x101168\nEXT V5.16B, V6.16B, V5.16B, #8 ; +0xac, 0x10116c\nINS V6.D[1], V7.D[0] ; +0xb0, 0x101170\nAND V3.16B, V3.16B, V1.16B ; +0xb4, 0x101174\nUZP1 V7.4S, V16.4S, V5.4S ; +0xb8, 0x101178\nUZP2 V5.4S, V16.4S, V5.4S ; +0xbc, 0x10117c\nUZP1 V16.4S, V4.4S, V6.4S ; +0xc0, 0x101180\nUZP2 V4.4S, V4.4S, V6.4S ; +0xc4, 0x101184\nFADD V3.4S, V3.4S, V4.4S ; +0xc8, 0x101188\nFADD V3.4S, V3.4S, V7.4S ; +0xcc, 0x10118c\nFADD V3.4S, V3.4S, V5.4S ; +0xd0, 0x101190\nFADD V3.4S, V16.4S, V3.4S ; +0xd4, 0x101194\nSUB W4, W4, #1 ; +0xd8, 0x101198\nSTR Q3, [X16],#0x10 ; +0xdc, 0x10119c\nADD X17, X17, #0x200 ; +0xe0, 0x1011a0\nCBNZ W4, loc_101138 ; +0xe4, 0x1011a4\nMOV W4, W12 ; +0xe8, 0x1011a8\nCBZ W4, loc_101A84 ; +0xec, 0x1011ac\nLDR W5, [X16] ; +0xf0, 0x1011b0\nLDR Q3, [X17],#0x80 ; +0xf4, 0x1011b4\nSUB W4, W4, #1 ; +0xf8, 0x1011b8\nAND W5, W5, W9 ; +0xfc, 0x1011bc\nFMUL V3.4S, V3.4S, V2.4S ; +0x100, 0x1011c0\nFADDP V3.4S, V3.4S, V3.4S ; +0x104, 0x1011c4\nFMOV S4, W5 ; +0x108, 0x1011c8\nFADDP S3, V3.2S ; +0x10c, 0x1011cc\nFADD S3, S3, S4 ; +0x110, 0x1011d0\nSTR S3, [X16],#4 ; +0x114, 0x1011d4\nCBNZ W4, loc_1011B0 ; +0x118, 0x1011d8\nB loc_101A84 ; +0x11c, 0x1011dc\nLDP Q2, Q3, [X0]; jumptable 000000000010111C cases 4-7 ; +0x120, 0x1011e0\nMOV X16, X1 ; +0x124, 0x1011e4\nMOV X17, X3 ; +0x128, 0x1011e8\nMOV W4, W11 ; +0x12c, 0x1011ec\nAND V3.16B, V3.16B, V0.16B ; +0x130, 0x1011f0\nCBZ W4, loc_101278 ; +0x134, 0x1011f4\nLDP Q5, Q6, [X17] ; +0x138, 0x1011f8\nLDP Q7, Q16, [X17,#0x80] ; +0x13c, 0x1011fc\nLDP Q17, Q18, [X17,#0x100] ; +0x140, 0x101200\nLDP Q19, Q20, [X17,#0x180] ; +0x144, 0x101204\nLDR Q4, [X16] ; +0x148, 0x101208\nFMUL V5.4S, V5.4S, V2.4S ; +0x14c, 0x10120c\nFMUL V7.4S, V7.4S, V2.4S ; +0x150, 0x101210\nFMUL V17.4S, V17.4S, V2.4S ; +0x154, 0x101214\nFMUL V19.4S, V19.4S, V2.4S ; +0x158, 0x101218\nFMLA V5.4S, V3.4S, V6.4S ; +0x15c, 0x10121c\nFMLA V7.4S, V3.4S, V16.4S ; +0x160, 0x101220\nFMLA V17.4S, V3.4S, V18.4S ; +0x164, 0x101224\nFMLA V19.4S, V3.4S, V20.4S ; +0x168, 0x101228\nEXT V6.16B, V7.16B, V5.16B, #8 ; +0x16c, 0x10122c\nEXT V16.16B, V19.16B, V17.16B, #8 ; +0x170, 0x101230\nEXT V6.16B, V5.16B, V6.16B, #8 ; +0x174, 0x101234\nEXT V16.16B, V17.16B, V16.16B, #8 ; +0x178, 0x101238\nINS V5.D[1], V7.D[0] ; +0x17c, 0x10123c\nINS V17.D[1], V19.D[0] ; +0x180, 0x101240\nAND V4.16B, V4.16B, V1.16B ; +0x184, 0x101244\nUZP1 V7.4S, V6.4S, V16.4S ; +0x188, 0x101248\nUZP2 V6.4S, V6.4S, V16.4S ; +0x18c, 0x10124c\nUZP1 V16.4S, V5.4S, V17.4S ; +0x190, 0x101250\nUZP2 V5.4S, V5.4S, V17.4S ; +0x194, 0x101254\nFADD V4.4S, V4.4S, V5.4S ; +0x198, 0x101258\nFADD V4.4S, V4.4S, V7.4S ; +0x19c, 0x10125c\nFADD V4.4S, V4.4S, V6.4S ; +0x1a0, 0x101260\nFADD V4.4S, V16.4S, V4.4S ; +0x1a4, 0x101264\nSUB W4, W4, #1 ; +0x1a8, 0x101268\nSTR Q4, [X16],#0x10 ; +0x1ac, 0x10126c\nADD X17, X17, #0x200 ; +0x1b0, 0x101270\nCBNZ W4, loc_1011F8 ; +0x1b4, 0x101274\nMOV W4, W12 ; +0x1b8, 0x101278\nCBZ W4, loc_101A84 ; +0x1bc, 0x10127c\nLDP Q4, Q5, [X17],#0x80 ; +0x1c0, 0x101280\nLDR W5, [X16] ; +0x1c4, 0x101284\nSUB W4, W4, #1 ; +0x1c8, 0x101288\nFMUL V4.4S, V4.4S, V2.4S ; +0x1cc, 0x10128c\nFMLA V4.4S, V3.4S, V5.4S ; +0x1d0, 0x101290\nAND W5, W5, W9 ; +0x1d4, 0x101294\nFADDP V4.4S, V4.4S, V4.4S ; +0x1d8, 0x101298\nFMOV S5, W5 ; +0x1dc, 0x10129c\nFADDP S4, V4.2S ; +0x1e0, 0x1012a0\nFADD S4, S4, S5 ; +0x1e4, 0x1012a4\nSTR S4, [X16],#4 ; +0x1e8, 0x1012a8\nCBNZ W4, loc_101280 ; +0x1ec, 0x1012ac\nB loc_101A84 ; +0x1f0, 0x1012b0\nLDP Q3, Q4, [X0,#0x10]; jumptable 000000000010111C cases 8-11 ; +0x1f4, 0x1012b4\nLDR Q2, [X0] ; +0x1f8, 0x1012b8\nMOV X16, X1 ; +0x1fc, 0x1012bc\nMOV X17, X3 ; +0x200, 0x1012c0\nAND V4.16B, V4.16B, V0.16B ; +0x204, 0x1012c4\nMOV W4, W11 ; +0x208, 0x1012c8\nCBZ W4, loc_101370 ; +0x20c, 0x1012cc\nLDP Q6, Q7, [X17] ; +0x210, 0x1012d0\nLDP Q16, Q17, [X17,#0x80] ; +0x214, 0x1012d4\nLDP Q18, Q19, [X17,#0x100] ; +0x218, 0x1012d8\nLDP Q20, Q21, [X17,#0x180] ; +0x21c, 0x1012dc\nFMUL V6.4S, V6.4S, V2.4S ; +0x220, 0x1012e0\nFMUL V16.4S, V16.4S, V2.4S ; +0x224, 0x1012e4\nFMUL V18.4S, V18.4S, V2.4S ; +0x228, 0x1012e8\nFMUL V20.4S, V20.4S, V2.4S ; +0x22c, 0x1012ec\nFMLA V6.4S, V3.4S, V7.4S ; +0x230, 0x1012f0\nLDR Q7, [X17,#0x20] ; +0x234, 0x1012f4\nFMLA V16.4S, V3.4S, V17.4S ; +0x238, 0x1012f8\nLDR Q17, [X17,#0xA0] ; +0x23c, 0x1012fc\nFMLA V18.4S, V3.4S, V19.4S ; +0x240, 0x101300\nLDR Q19, [X17,#0x120] ; +0x244, 0x101304\nFMLA V20.4S, V3.4S, V21.4S ; +0x248, 0x101308\nLDR Q21, [X17,#0x1A0] ; +0x24c, 0x10130c\nLDR Q5, [X16] ; +0x250, 0x101310\nFMLA V6.4S, V4.4S, V7.4S ; +0x254, 0x101314\nFMLA V16.4S, V4.4S, V17.4S ; +0x258, 0x101318\nFMLA V18.4S, V4.4S, V19.4S ; +0x25c, 0x10131c\nFMLA V20.4S, V4.4S, V21.4S ; +0x260, 0x101320\nEXT V7.16B, V16.16B, V6.16B, #8 ; +0x264, 0x101324\nEXT V17.16B, V20.16B, V18.16B, #8 ; +0x268, 0x101328\nEXT V7.16B, V6.16B, V7.16B, #8 ; +0x26c, 0x10132c\nEXT V17.16B, V18.16B, V17.16B, #8 ; +0x270, 0x101330\nINS V6.D[1], V16.D[0] ; +0x274, 0x101334\nINS V18.D[1], V20.D[0] ; +0x278, 0x101338\nAND V5.16B, V5.16B, V1.16B ; +0x27c, 0x10133c\nUZP1 V16.4S, V7.4S, V17.4S ; +0x280, 0x101340\nUZP2 V7.4S, V7.4S, V17.4S ; +0x284, 0x101344\nUZP1 V17.4S, V6.4S, V18.4S ; +0x288, 0x101348\nUZP2 V6.4S, V6.4S, V18.4S ; +0x28c, 0x10134c\nFADD V5.4S, V5.4S, V6.4S ; +0x290, 0x101350\nFADD V5.4S, V5.4S, V16.4S ; +0x294, 0x101354\nFADD V5.4S, V5.4S, V7.4S ; +0x298, 0x101358\nFADD V5.4S, V17.4S, V5.4S ; +0x29c, 0x10135c\nSUB W4, W4, #1 ; +0x2a0, 0x101360\nSTR Q5, [X16],#0x10 ; +0x2a4, 0x101364\nADD X17, X17, #0x200 ; +0x2a8, 0x101368\nCBNZ W4, loc_1012D0 ; +0x2ac, 0x10136c\nMOV W4, W12 ; +0x2b0, 0x101370\nCBZ W4, loc_101A84 ; +0x2b4, 0x101374\nLDP Q5, Q6, [X17] ; +0x2b8, 0x101378\nLDR Q7, [X17,#0x20] ; +0x2bc, 0x10137c\nLDR W5, [X16] ; +0x2c0, 0x101380\nSUB W4, W4, #1 ; +0x2c4, 0x101384\nFMUL V5.4S, V5.4S, V2.4S ; +0x2c8, 0x101388\nFMLA V5.4S, V3.4S, V6.4S ; +0x2cc, 0x10138c\nFMLA V5.4S, V4.4S, V7.4S ; +0x2d0, 0x101390\nAND W5, W5, W9 ; +0x2d4, 0x101394\nFADDP V5.4S, V5.4S, V5.4S ; +0x2d8, 0x101398\nFMOV S6, W5 ; +0x2dc, 0x10139c\nFADDP S5, V5.2S ; +0x2e0, 0x1013a0\nFADD S5, S5, S6 ; +0x2e4, 0x1013a4\nSTR S5, [X16],#4 ; +0x2e8, 0x1013a8\nADD X17, X17, #0x80 ; +0x2ec, 0x1013ac\nCBNZ W4, loc_101378 ; +0x2f0, 0x1013b0\nB loc_101A84 ; +0x2f4, 0x1013b4\nLDP Q2, Q5, [X0,#0x20]; jumptable 000000000010111C cases 12-15 ; +0x2f8, 0x1013b8\nLDP Q3, Q4, [X0] ; +0x2fc, 0x1013bc\nMOV X16, X1 ; +0x300, 0x1013c0\nMOV X17, X3 ; +0x304, 0x1013c4\nAND V5.16B, V5.16B, V0.16B ; +0x308, 0x1013c8\nMOV W4, W11 ; +0x30c, 0x1013cc\nCBZ W4, loc_101484 ; +0x310, 0x1013d0\nLDP Q19, Q20, [X17,#0x100] ; +0x314, 0x1013d4\nLDP Q21, Q22, [X17,#0x180] ; +0x318, 0x1013d8\nLDP Q7, Q16, [X17] ; +0x31c, 0x1013dc\nLDP Q17, Q18, [X17,#0x80] ; +0x320, 0x1013e0\nFMUL V19.4S, V19.4S, V3.4S ; +0x324, 0x1013e4\nFMUL V21.4S, V21.4S, V3.4S ; +0x328, 0x1013e8\nFMLA V19.4S, V4.4S, V20.4S ; +0x32c, 0x1013ec\nFMLA V21.4S, V4.4S, V22.4S ; +0x330, 0x1013f0\nLDP Q20, Q22, [X17,#0x20] ; +0x334, 0x1013f4\nFMUL V7.4S, V7.4S, V3.4S ; +0x338, 0x1013f8\nFMLA V7.4S, V4.4S, V16.4S ; +0x33c, 0x1013fc\nFMUL V17.4S, V17.4S, V3.4S ; +0x340, 0x101400\nFMLA V7.4S, V2.4S, V20.4S ; +0x344, 0x101404\nLDP Q23, Q20, [X17,#0xA0] ; +0x348, 0x101408\nFMLA V17.4S, V4.4S, V18.4S ; +0x34c, 0x10140c\nLDR Q6, [X16] ; +0x350, 0x101410\nFMLA V7.4S, V5.4S, V22.4S ; +0x354, 0x101414\nFMLA V17.4S, V2.4S, V23.4S ; +0x358, 0x101418\nLDP Q16, Q23, [X17,#0x120] ; +0x35c, 0x10141c\nFMLA V17.4S, V5.4S, V20.4S ; +0x360, 0x101420\nAND V6.16B, V6.16B, V1.16B ; +0x364, 0x101424\nSUB W4, W4, #1 ; +0x368, 0x101428\nFMLA V19.4S, V2.4S, V16.4S ; +0x36c, 0x10142c\nLDP Q18, Q16, [X17,#0x1A0] ; +0x370, 0x101430\nFMLA V19.4S, V5.4S, V23.4S ; +0x374, 0x101434\nADD X17, X17, #0x200 ; +0x378, 0x101438\nFMLA V21.4S, V2.4S, V18.4S ; +0x37c, 0x10143c\nFMLA V21.4S, V5.4S, V16.4S ; +0x380, 0x101440\nEXT V16.16B, V17.16B, V7.16B, #8 ; +0x384, 0x101444\nEXT V18.16B, V21.16B, V19.16B, #8 ; +0x388, 0x101448\nEXT V16.16B, V7.16B, V16.16B, #8 ; +0x38c, 0x10144c\nEXT V18.16B, V19.16B, V18.16B, #8 ; +0x390, 0x101450\nINS V7.D[1], V17.D[0] ; +0x394, 0x101454\nINS V19.D[1], V21.D[0] ; +0x398, 0x101458\nUZP1 V17.4S, V16.4S, V18.4S ; +0x39c, 0x10145c\nUZP2 V16.4S, V16.4S, V18.4S ; +0x3a0, 0x101460\nUZP1 V18.4S, V7.4S, V19.4S ; +0x3a4, 0x101464\nUZP2 V7.4S, V7.4S, V19.4S ; +0x3a8, 0x101468\nFADD V6.4S, V6.4S, V7.4S ; +0x3ac, 0x10146c\nFADD V6.4S, V6.4S, V17.4S ; +0x3b0, 0x101470\nFADD V6.4S, V6.4S, V16.4S ; +0x3b4, 0x101474\nFADD V6.4S, V18.4S, V6.4S ; +0x3b8, 0x101478\nSTR Q6, [X16],#0x10 ; +0x3bc, 0x10147c\nCBNZ W4, loc_1013D4 ; +0x3c0, 0x101480\nMOV W4, W12 ; +0x3c4, 0x101484\nCBZ W4, loc_101A84 ; +0x3c8, 0x101488\nLDP Q6, Q7, [X17] ; +0x3cc, 0x10148c\nLDR W5, [X16] ; +0x3d0, 0x101490\nSUB W4, W4, #1 ; +0x3d4, 0x101494\nFMUL V6.4S, V6.4S, V3.4S ; +0x3d8, 0x101498\nFMLA V6.4S, V4.4S, V7.4S ; +0x3dc, 0x10149c\nLDP Q16, Q7, [X17,#0x20] ; +0x3e0, 0x1014a0\nAND W5, W5, W9 ; +0x3e4, 0x1014a4\nADD X17, X17, #0x80 ; +0x3e8, 0x1014a8\nFMLA V6.4S, V2.4S, V16.4S ; +0x3ec, 0x1014ac\nFMLA V6.4S, V5.4S, V7.4S ; +0x3f0, 0x1014b0\nFADDP V6.4S, V6.4S, V6.4S ; +0x3f4, 0x1014b4\nFMOV S7, W5 ; +0x3f8, 0x1014b8\nFADDP S6, V6.2S ; +0x3fc, 0x1014bc\nFADD S6, S6, S7 ; +0x400, 0x1014c0\nSTR S6, [X16],#4 ; +0x404, 0x1014c4\nCBNZ W4, loc_10148C ; +0x408, 0x1014c8\nB loc_101A84 ; +0x40c, 0x1014cc\nLDP Q5, Q6, [X0,#0x30]; jumptable 000000000010111C cases 16-19 ; +0x410, 0x1014d0\nLDP Q2, Q3, [X0] ; +0x414, 0x1014d4\nLDR Q4, [X0,#0x20] ; +0x418, 0x1014d8\nMOV X16, X1 ; +0x41c, 0x1014dc\nAND V6.16B, V6.16B, V0.16B ; +0x420, 0x1014e0\nMOV X17, X3 ; +0x424, 0x1014e4\nMOV W4, W11 ; +0x428, 0x1014e8\nCBZ W4, loc_1015C0 ; +0x42c, 0x1014ec\nLDP Q7, Q17, [X17] ; +0x430, 0x1014f0\nLDP Q18, Q19, [X17,#0x80] ; +0x434, 0x1014f4\nLDP Q20, Q21, [X17,#0x100] ; +0x438, 0x1014f8\nLDP Q22, Q23, [X17,#0x180] ; +0x43c, 0x1014fc\nFMUL V16.4S, V7.4S, V2.4S ; +0x440, 0x101500\nFMUL V7.4S, V18.4S, V2.4S ; +0x444, 0x101504\nFMLA V7.4S, V3.4S, V19.4S ; +0x448, 0x101508\nFMUL V19.4S, V20.4S, V2.4S ; +0x44c, 0x10150c\nFMLA V19.4S, V3.4S, V21.4S ; +0x450, 0x101510\nFMUL V21.4S, V22.4S, V2.4S ; +0x454, 0x101514\nFMLA V16.4S, V3.4S, V17.4S ; +0x458, 0x101518\nFMLA V21.4S, V3.4S, V23.4S ; +0x45c, 0x10151c\nLDP Q20, Q22, [X17,#0x20] ; +0x460, 0x101520\nLDP Q17, Q23, [X17,#0x120] ; +0x464, 0x101524\nSUB W4, W4, #1 ; +0x468, 0x101528\nFMLA V16.4S, V4.4S, V20.4S ; +0x46c, 0x10152c\nLDP Q24, Q20, [X17,#0xA0] ; +0x470, 0x101530\nFMLA V19.4S, V4.4S, V17.4S ; +0x474, 0x101534\nLDP Q18, Q17, [X17,#0x1A0] ; +0x478, 0x101538\nFMLA V16.4S, V5.4S, V22.4S ; +0x47c, 0x10153c\nFMLA V7.4S, V4.4S, V24.4S ; +0x480, 0x101540\nLDR Q22, [X17,#0x40] ; +0x484, 0x101544\nFMLA V21.4S, V4.4S, V18.4S ; +0x488, 0x101548\nFMLA V7.4S, V5.4S, V20.4S ; +0x48c, 0x10154c\nLDR Q20, [X17,#0xC0] ; +0x490, 0x101550\nFMLA V19.4S, V5.4S, V23.4S ; +0x494, 0x101554\nLDR Q23, [X17,#0x140] ; +0x498, 0x101558\nFMLA V21.4S, V5.4S, V17.4S ; +0x49c, 0x10155c\nLDR Q17, [X17,#0x1C0] ; +0x4a0, 0x101560\nLDR Q18, [X16] ; +0x4a4, 0x101564\nFMLA V16.4S, V6.4S, V22.4S ; +0x4a8, 0x101568\nFMLA V7.4S, V6.4S, V20.4S ; +0x4ac, 0x10156c\nFMLA V19.4S, V6.4S, V23.4S ; +0x4b0, 0x101570\nFMLA V21.4S, V6.4S, V17.4S ; +0x4b4, 0x101574\nEXT V17.16B, V7.16B, V16.16B, #8 ; +0x4b8, 0x101578\nEXT V20.16B, V21.16B, V19.16B, #8 ; +0x4bc, 0x10157c\nEXT V17.16B, V16.16B, V17.16B, #8 ; +0x4c0, 0x101580\nEXT V20.16B, V19.16B, V20.16B, #8 ; +0x4c4, 0x101584\nINS V16.D[1], V7.D[0] ; +0x4c8, 0x101588\nINS V19.D[1], V21.D[0] ; +0x4cc, 0x10158c\nAND V18.16B, V18.16B, V1.16B ; +0x4d0, 0x101590\nUZP1 V7.4S, V17.4S, V20.4S ; +0x4d4, 0x101594\nUZP2 V17.4S, V17.4S, V20.4S ; +0x4d8, 0x101598\nUZP1 V20.4S, V16.4S, V19.4S ; +0x4dc, 0x10159c\nUZP2 V16.4S, V16.4S, V19.4S ; +0x4e0, 0x1015a0\nFADD V16.4S, V18.4S, V16.4S ; +0x4e4, 0x1015a4\nFADD V7.4S, V16.4S, V7.4S ; +0x4e8, 0x1015a8\nFADD V7.4S, V7.4S, V17.4S ; +0x4ec, 0x1015ac\nFADD V7.4S, V20.4S, V7.4S ; +0x4f0, 0x1015b0\nSTR Q7, [X16],#0x10 ; +0x4f4, 0x1015b4\nADD X17, X17, #0x200 ; +0x4f8, 0x1015b8\nCBNZ W4, loc_1014F0 ; +0x4fc, 0x1015bc\nMOV W4, W12 ; +0x500, 0x1015c0\nCBZ W4, loc_101A84 ; +0x504, 0x1015c4\nLDP Q7, Q16, [X17] ; +0x508, 0x1015c8\nLDR W5, [X16] ; +0x50c, 0x1015cc\nSUB W4, W4, #1 ; +0x510, 0x1015d0\nFMUL V7.4S, V7.4S, V2.4S ; +0x514, 0x1015d4\nFMLA V7.4S, V3.4S, V16.4S ; +0x518, 0x1015d8\nLDP Q17, Q16, [X17,#0x20] ; +0x51c, 0x1015dc\nAND W5, W5, W9 ; +0x520, 0x1015e0\nFMLA V7.4S, V4.4S, V17.4S ; +0x524, 0x1015e4\nLDR Q17, [X17,#0x40] ; +0x528, 0x1015e8\nFMLA V7.4S, V5.4S, V16.4S ; +0x52c, 0x1015ec\nFMOV S16, W5 ; +0x530, 0x1015f0\nADD X17, X17, #0x80 ; +0x534, 0x1015f4\nFMLA V7.4S, V6.4S, V17.4S ; +0x538, 0x1015f8\nFADDP V7.4S, V7.4S, V7.4S ; +0x53c, 0x1015fc\nFADDP S7, V7.2S ; +0x540, 0x101600\nFADD S7, S7, S16 ; +0x544, 0x101604\nSTR S7, [X16],#4 ; +0x548, 0x101608\nCBNZ W4, loc_1015C8 ; +0x54c, 0x10160c\nB loc_101A84 ; +0x550, 0x101610\nLDP Q4, Q7, [X0,#0x40]; jumptable 000000000010111C cases 20-23 ; +0x554, 0x101614\nLDP Q2, Q3, [X0] ; +0x558, 0x101618\nLDP Q5, Q6, [X0,#0x20] ; +0x55c, 0x10161c\nMOV X16, X1 ; +0x560, 0x101620\nAND V7.16B, V7.16B, V0.16B ; +0x564, 0x101624\nMOV X17, X3 ; +0x568, 0x101628\nMOV W4, W11 ; +0x56c, 0x10162c\nCBZ W4, loc_101714 ; +0x570, 0x101630\nLDP Q17, Q19, [X17] ; +0x574, 0x101634\nLDP Q22, Q23, [X17,#0x100] ; +0x578, 0x101638\nLDP Q20, Q21, [X17,#0x80] ; +0x57c, 0x10163c\nLDP Q24, Q25, [X17,#0x180] ; +0x580, 0x101640\nFMUL V18.4S, V17.4S, V2.4S ; +0x584, 0x101644\nFMLA V18.4S, V3.4S, V19.4S ; +0x588, 0x101648\nFMUL V19.4S, V22.4S, V2.4S ; +0x58c, 0x10164c\nFMLA V19.4S, V3.4S, V23.4S ; +0x590, 0x101650\nLDP Q22, Q23, [X17,#0x20] ; +0x594, 0x101654\nFMUL V17.4S, V20.4S, V2.4S ; +0x598, 0x101658\nFMUL V20.4S, V24.4S, V2.4S ; +0x59c, 0x10165c\nFMLA V17.4S, V3.4S, V21.4S ; +0x5a0, 0x101660\nFMLA V20.4S, V3.4S, V25.4S ; +0x5a4, 0x101664\nFMLA V18.4S, V5.4S, V22.4S ; +0x5a8, 0x101668\nLDP Q26, Q22, [X17,#0xA0] ; +0x5ac, 0x10166c\nLDP Q21, Q25, [X17,#0x1A0] ; +0x5b0, 0x101670\nFMLA V18.4S, V6.4S, V23.4S ; +0x5b4, 0x101674\nLDP Q27, Q24, [X17,#0x120] ; +0x5b8, 0x101678\nFMLA V17.4S, V5.4S, V26.4S ; +0x5bc, 0x10167c\nFMLA V20.4S, V5.4S, V21.4S ; +0x5c0, 0x101680\nFMLA V17.4S, V6.4S, V22.4S ; +0x5c4, 0x101684\nFMLA V20.4S, V6.4S, V25.4S ; +0x5c8, 0x101688\nLDP Q22, Q25, [X17,#0x40] ; +0x5cc, 0x10168c\nFMLA V19.4S, V5.4S, V27.4S ; +0x5d0, 0x101690\nFMLA V19.4S, V6.4S, V24.4S ; +0x5d4, 0x101694\nLDR Q16, [X16] ; +0x5d8, 0x101698\nFMLA V18.4S, V4.4S, V22.4S ; +0x5dc, 0x10169c\nLDP Q21, Q22, [X17,#0xC0] ; +0x5e0, 0x1016a0\nFMLA V18.4S, V7.4S, V25.4S ; +0x5e4, 0x1016a4\nAND V16.16B, V16.16B, V1.16B ; +0x5e8, 0x1016a8\nSUB W4, W4, #1 ; +0x5ec, 0x1016ac\nFMLA V17.4S, V4.4S, V21.4S ; +0x5f0, 0x1016b0\nLDP Q23, Q21, [X17,#0x140] ; +0x5f4, 0x1016b4\nFMLA V17.4S, V7.4S, V22.4S ; +0x5f8, 0x1016b8\nFMLA V19.4S, V4.4S, V23.4S ; +0x5fc, 0x1016bc\nLDP Q24, Q23, [X17,#0x1C0] ; +0x600, 0x1016c0\nFMLA V19.4S, V7.4S, V21.4S ; +0x604, 0x1016c4\nEXT V21.16B, V17.16B, V18.16B, #8 ; +0x608, 0x1016c8\nEXT V21.16B, V18.16B, V21.16B, #8 ; +0x60c, 0x1016cc\nFMLA V20.4S, V4.4S, V24.4S ; +0x610, 0x1016d0\nFMLA V20.4S, V7.4S, V23.4S ; +0x614, 0x1016d4\nEXT V22.16B, V20.16B, V19.16B, #8 ; +0x618, 0x1016d8\nEXT V22.16B, V19.16B, V22.16B, #8 ; +0x61c, 0x1016dc\nINS V18.D[1], V17.D[0] ; +0x620, 0x1016e0\nINS V19.D[1], V20.D[0] ; +0x624, 0x1016e4\nUZP1 V17.4S, V21.4S, V22.4S ; +0x628, 0x1016e8\nUZP2 V20.4S, V21.4S, V22.4S ; +0x62c, 0x1016ec\nUZP1 V21.4S, V18.4S, V19.4S ; +0x630, 0x1016f0\nUZP2 V18.4S, V18.4S, V19.4S ; +0x634, 0x1016f4\nFADD V16.4S, V16.4S, V18.4S ; +0x638, 0x1016f8\nFADD V16.4S, V16.4S, V17.4S ; +0x63c, 0x1016fc\nFADD V16.4S, V16.4S, V20.4S ; +0x640, 0x101700\nFADD V16.4S, V21.4S, V16.4S ; +0x644, 0x101704\nSTR Q16, [X16],#0x10 ; +0x648, 0x101708\nADD X17, X17, #0x200 ; +0x64c, 0x10170c\nCBNZ W4, loc_101634 ; +0x650, 0x101710\nMOV W4, W12 ; +0x654, 0x101714\nCBZ W4, loc_101A84 ; +0x658, 0x101718\nLDP Q16, Q17, [X17] ; +0x65c, 0x10171c\nLDR W5, [X16] ; +0x660, 0x101720\nSUB W4, W4, #1 ; +0x664, 0x101724\nFMUL V16.4S, V16.4S, V2.4S ; +0x668, 0x101728\nFMLA V16.4S, V3.4S, V17.4S ; +0x66c, 0x10172c\nLDP Q18, Q17, [X17,#0x20] ; +0x670, 0x101730\nAND W5, W5, W9 ; +0x674, 0x101734\nFMLA V16.4S, V5.4S, V18.4S ; +0x678, 0x101738\nFMLA V16.4S, V6.4S, V17.4S ; +0x67c, 0x10173c\nLDP Q18, Q17, [X17,#0x40] ; +0x680, 0x101740\nADD X17, X17, #0x80 ; +0x684, 0x101744\nFMLA V16.4S, V4.4S, V18.4S ; +0x688, 0x101748\nFMLA V16.4S, V7.4S, V17.4S ; +0x68c, 0x10174c\nFADDP V16.4S, V16.4S, V16.4S ; +0x690, 0x101750\nFMOV S17, W5 ; +0x694, 0x101754\nFADDP S16, V16.2S ; +0x698, 0x101758\nFADD S16, S16, S17 ; +0x69c, 0x10175c\nSTR S16, [X16],#4 ; +0x6a0, 0x101760\nCBNZ W4, loc_10171C ; +0x6a4, 0x101764\nB loc_101A84 ; +0x6a8, 0x101768\nLDP Q7, Q16, [X0,#0x50]; jumptable 000000000010111C cases 24-27 ; +0x6ac, 0x10176c\nLDP Q2, Q3, [X0] ; +0x6b0, 0x101770\nLDP Q4, Q5, [X0,#0x20] ; +0x6b4, 0x101774\nLDR Q6, [X0,#0x40] ; +0x6b8, 0x101778\nAND V16.16B, V16.16B, V0.16B ; +0x6bc, 0x10177c\nMOV X16, X1 ; +0x6c0, 0x101780\nMOV X17, X3 ; +0x6c4, 0x101784\nMOV W4, W11 ; +0x6c8, 0x101788\nCBZ W4, loc_101890 ; +0x6cc, 0x10178c\nLDP Q17, Q19, [X17] ; +0x6d0, 0x101790\nLDP Q22, Q23, [X17,#0x100] ; +0x6d4, 0x101794\nLDP Q20, Q21, [X17,#0x80] ; +0x6d8, 0x101798\nLDP Q24, Q25, [X17,#0x180] ; +0x6dc, 0x10179c\nFMUL V18.4S, V17.4S, V2.4S ; +0x6e0, 0x1017a0\nFMLA V18.4S, V3.4S, V19.4S ; +0x6e4, 0x1017a4\nFMUL V19.4S, V22.4S, V2.4S ; +0x6e8, 0x1017a8\nFMLA V19.4S, V3.4S, V23.4S ; +0x6ec, 0x1017ac\nLDP Q22, Q23, [X17,#0x20] ; +0x6f0, 0x1017b0\nFMUL V17.4S, V20.4S, V2.4S ; +0x6f4, 0x1017b4\nFMUL V20.4S, V24.4S, V2.4S ; +0x6f8, 0x1017b8\nFMLA V17.4S, V3.4S, V21.4S ; +0x6fc, 0x1017bc\nFMLA V20.4S, V3.4S, V25.4S ; +0x700, 0x1017c0\nFMLA V18.4S, V4.4S, V22.4S ; +0x704, 0x1017c4\nLDP Q26, Q22, [X17,#0xA0] ; +0x708, 0x1017c8\nLDP Q21, Q25, [X17,#0x1A0] ; +0x70c, 0x1017cc\nFMLA V18.4S, V5.4S, V23.4S ; +0x710, 0x1017d0\nLDP Q27, Q24, [X17,#0x120] ; +0x714, 0x1017d4\nFMLA V17.4S, V4.4S, V26.4S ; +0x718, 0x1017d8\nFMLA V20.4S, V4.4S, V21.4S ; +0x71c, 0x1017dc\nFMLA V17.4S, V5.4S, V22.4S ; +0x720, 0x1017e0\nFMLA V20.4S, V5.4S, V25.4S ; +0x724, 0x1017e4\nLDP Q22, Q25, [X17,#0x40] ; +0x728, 0x1017e8\nFMLA V19.4S, V4.4S, V27.4S ; +0x72c, 0x1017ec\nFMLA V19.4S, V5.4S, V24.4S ; +0x730, 0x1017f0\nSUB W4, W4, #1 ; +0x734, 0x1017f4\nFMLA V18.4S, V6.4S, V22.4S ; +0x738, 0x1017f8\nLDP Q21, Q22, [X17,#0xC0] ; +0x73c, 0x1017fc\nFMLA V18.4S, V7.4S, V25.4S ; +0x740, 0x101800\nLDR Q25, [X17,#0x60] ; +0x744, 0x101804\nFMLA V17.4S, V6.4S, V21.4S ; +0x748, 0x101808\nLDP Q23, Q21, [X17,#0x140] ; +0x74c, 0x10180c\nFMLA V17.4S, V7.4S, V22.4S ; +0x750, 0x101810\nLDR Q22, [X17,#0xE0] ; +0x754, 0x101814\nFMLA V18.4S, V16.4S, V25.4S ; +0x758, 0x101818\nFMLA V19.4S, V6.4S, V23.4S ; +0x75c, 0x10181c\nLDP Q24, Q23, [X17,#0x1C0] ; +0x760, 0x101820\nFMLA V19.4S, V7.4S, V21.4S ; +0x764, 0x101824\nLDR Q21, [X17,#0x160] ; +0x768, 0x101828\nFMLA V17.4S, V16.4S, V22.4S ; +0x76c, 0x10182c\nFMLA V20.4S, V6.4S, V24.4S ; +0x770, 0x101830\nFMLA V20.4S, V7.4S, V23.4S ; +0x774, 0x101834\nLDR Q23, [X17,#0x1E0] ; +0x778, 0x101838\nLDR Q24, [X16] ; +0x77c, 0x10183c\nFMLA V19.4S, V16.4S, V21.4S ; +0x780, 0x101840\nEXT V21.16B, V17.16B, V18.16B, #8 ; +0x784, 0x101844\nFMLA V20.4S, V16.4S, V23.4S ; +0x788, 0x101848\nEXT V22.16B, V20.16B, V19.16B, #8 ; +0x78c, 0x10184c\nEXT V21.16B, V18.16B, V21.16B, #8 ; +0x790, 0x101850\nEXT V22.16B, V19.16B, V22.16B, #8 ; +0x794, 0x101854\nINS V18.D[1], V17.D[0] ; +0x798, 0x101858\nINS V19.D[1], V20.D[0] ; +0x79c, 0x10185c\nAND V24.16B, V24.16B, V1.16B ; +0x7a0, 0x101860\nUZP1 V17.4S, V21.4S, V22.4S ; +0x7a4, 0x101864\nUZP2 V20.4S, V21.4S, V22.4S ; +0x7a8, 0x101868\nUZP1 V21.4S, V18.4S, V19.4S ; +0x7ac, 0x10186c\nUZP2 V18.4S, V18.4S, V19.4S ; +0x7b0, 0x101870\nFADD V18.4S, V24.4S, V18.4S ; +0x7b4, 0x101874\nFADD V17.4S, V18.4S, V17.4S ; +0x7b8, 0x101878\nFADD V17.4S, V17.4S, V20.4S ; +0x7bc, 0x10187c\nFADD V17.4S, V21.4S, V17.4S ; +0x7c0, 0x101880\nSTR Q17, [X16],#0x10 ; +0x7c4, 0x101884\nADD X17, X17, #0x200 ; +0x7c8, 0x101888\nCBNZ W4, loc_101790 ; +0x7cc, 0x10188c\nMOV W4, W12 ; +0x7d0, 0x101890\nCBZ W4, loc_101A84 ; +0x7d4, 0x101894\nLDP Q17, Q18, [X17] ; +0x7d8, 0x101898\nLDP Q19, Q20, [X17,#0x20] ; +0x7dc, 0x10189c\nLDR W5, [X16] ; +0x7e0, 0x1018a0\nSUB W4, W4, #1 ; +0x7e4, 0x1018a4\nFMUL V17.4S, V17.4S, V2.4S ; +0x7e8, 0x1018a8\nFMLA V17.4S, V3.4S, V18.4S ; +0x7ec, 0x1018ac\nFMLA V17.4S, V4.4S, V19.4S ; +0x7f0, 0x1018b0\nLDP Q18, Q19, [X17,#0x40] ; +0x7f4, 0x1018b4\nFMLA V17.4S, V5.4S, V20.4S ; +0x7f8, 0x1018b8\nAND W5, W5, W9 ; +0x7fc, 0x1018bc\nFMLA V17.4S, V6.4S, V18.4S ; +0x800, 0x1018c0\nLDR Q18, [X17,#0x60] ; +0x804, 0x1018c4\nFMLA V17.4S, V7.4S, V19.4S ; +0x808, 0x1018c8\nADD X17, X17, #0x80 ; +0x80c, 0x1018cc\nFMLA V17.4S, V16.4S, V18.4S ; +0x810, 0x1018d0\nFADDP V17.4S, V17.4S, V17.4S ; +0x814, 0x1018d4\nFMOV S18, W5 ; +0x818, 0x1018d8\nFADDP S17, V17.2S ; +0x81c, 0x1018dc\nFADD S17, S17, S18 ; +0x820, 0x1018e0\nSTR S17, [X16],#4 ; +0x824, 0x1018e4\nCBNZ W4, loc_101898 ; +0x828, 0x1018e8\nB loc_101A84 ; +0x82c, 0x1018ec\nLDP Q6, Q17, [X0,#0x60]; jumptable 000000000010111C cases 28-31 ; +0x830, 0x1018f0\nLDP Q2, Q3, [X0] ; +0x834, 0x1018f4\nLDP Q4, Q5, [X0,#0x20] ; +0x838, 0x1018f8\nLDP Q7, Q16, [X0,#0x40] ; +0x83c, 0x1018fc\nAND V17.16B, V17.16B, V0.16B ; +0x840, 0x101900\nMOV X16, X1 ; +0x844, 0x101904\nMOV X17, X3 ; +0x848, 0x101908\nMOV W4, W11 ; +0x84c, 0x10190c\nCBZ W4, loc_101A24 ; +0x850, 0x101910\nLDP Q19, Q21, [X17] ; +0x854, 0x101914\nLDP Q24, Q25, [X17,#0x100] ; +0x858, 0x101918\nLDP Q22, Q23, [X17,#0x80] ; +0x85c, 0x10191c\nLDP Q26, Q27, [X17,#0x180] ; +0x860, 0x101920\nFMUL V20.4S, V19.4S, V2.4S ; +0x864, 0x101924\nFMLA V20.4S, V3.4S, V21.4S ; +0x868, 0x101928\nFMUL V21.4S, V24.4S, V2.4S ; +0x86c, 0x10192c\nFMLA V21.4S, V3.4S, V25.4S ; +0x870, 0x101930\nLDP Q24, Q25, [X17,#0x20] ; +0x874, 0x101934\nFMUL V19.4S, V22.4S, V2.4S ; +0x878, 0x101938\nFMUL V22.4S, V26.4S, V2.4S ; +0x87c, 0x10193c\nFMLA V19.4S, V3.4S, V23.4S ; +0x880, 0x101940\nFMLA V22.4S, V3.4S, V27.4S ; +0x884, 0x101944\nFMLA V20.4S, V4.4S, V24.4S ; +0x888, 0x101948\nLDP Q28, Q24, [X17,#0xA0] ; +0x88c, 0x10194c\nLDP Q23, Q27, [X17,#0x1A0] ; +0x890, 0x101950\nFMLA V20.4S, V5.4S, V25.4S ; +0x894, 0x101954\nLDP Q29, Q26, [X17,#0x120] ; +0x898, 0x101958\nFMLA V19.4S, V4.4S, V28.4S ; +0x89c, 0x10195c\nFMLA V22.4S, V4.4S, V23.4S ; +0x8a0, 0x101960\nFMLA V19.4S, V5.4S, V24.4S ; +0x8a4, 0x101964\nFMLA V22.4S, V5.4S, V27.4S ; +0x8a8, 0x101968\nLDP Q24, Q27, [X17,#0x40] ; +0x8ac, 0x10196c\nFMLA V21.4S, V4.4S, V29.4S ; +0x8b0, 0x101970\nFMLA V21.4S, V5.4S, V26.4S ; +0x8b4, 0x101974\nLDR Q18, [X16] ; +0x8b8, 0x101978\nFMLA V20.4S, V7.4S, V24.4S ; +0x8bc, 0x10197c\nLDP Q23, Q24, [X17,#0xC0] ; +0x8c0, 0x101980\nFMLA V20.4S, V16.4S, V27.4S ; +0x8c4, 0x101984\nAND V18.16B, V18.16B, V1.16B ; +0x8c8, 0x101988\nSUB W4, W4, #1 ; +0x8cc, 0x10198c\nFMLA V19.4S, V7.4S, V23.4S ; +0x8d0, 0x101990\nLDP Q25, Q23, [X17,#0x140] ; +0x8d4, 0x101994\nFMLA V19.4S, V16.4S, V24.4S ; +0x8d8, 0x101998\nFMLA V21.4S, V7.4S, V25.4S ; +0x8dc, 0x10199c\nLDP Q26, Q25, [X17,#0x1C0] ; +0x8e0, 0x1019a0\nFMLA V21.4S, V16.4S, V23.4S ; +0x8e4, 0x1019a4\nFMLA V22.4S, V7.4S, V26.4S ; +0x8e8, 0x1019a8\nFMLA V22.4S, V16.4S, V25.4S ; +0x8ec, 0x1019ac\nLDP Q23, Q25, [X17,#0x60] ; +0x8f0, 0x1019b0\nFMLA V20.4S, V6.4S, V23.4S ; +0x8f4, 0x1019b4\nLDP Q26, Q23, [X17,#0xE0] ; +0x8f8, 0x1019b8\nFMLA V20.4S, V17.4S, V25.4S ; +0x8fc, 0x1019bc\nFMLA V19.4S, V6.4S, V26.4S ; +0x900, 0x1019c0\nLDP Q27, Q26, [X17,#0x160] ; +0x904, 0x1019c4\nFMLA V19.4S, V17.4S, V23.4S ; +0x908, 0x1019c8\nEXT V23.16B, V19.16B, V20.16B, #8 ; +0x90c, 0x1019cc\nEXT V23.16B, V20.16B, V23.16B, #8 ; +0x910, 0x1019d0\nFMLA V21.4S, V6.4S, V27.4S ; +0x914, 0x1019d4\nLDP Q24, Q27, [X17,#0x1E0] ; +0x918, 0x1019d8\nFMLA V21.4S, V17.4S, V26.4S ; +0x91c, 0x1019dc\nINS V20.D[1], V19.D[0] ; +0x920, 0x1019e0\nADD X17, X17, #0x200 ; +0x924, 0x1019e4\nFMLA V22.4S, V6.4S, V24.4S ; +0x928, 0x1019e8\nFMLA V22.4S, V17.4S, V27.4S ; +0x92c, 0x1019ec\nEXT V24.16B, V22.16B, V21.16B, #8 ; +0x930, 0x1019f0\nEXT V24.16B, V21.16B, V24.16B, #8 ; +0x934, 0x1019f4\nINS V21.D[1], V22.D[0] ; +0x938, 0x1019f8\nUZP1 V19.4S, V23.4S, V24.4S ; +0x93c, 0x1019fc\nUZP2 V22.4S, V23.4S, V24.4S ; +0x940, 0x101a00\nUZP1 V23.4S, V20.4S, V21.4S ; +0x944, 0x101a04\nUZP2 V20.4S, V20.4S, V21.4S ; +0x948, 0x101a08\nFADD V18.4S, V18.4S, V20.4S ; +0x94c, 0x101a0c\nFADD V18.4S, V18.4S, V19.4S ; +0x950, 0x101a10\nFADD V18.4S, V18.4S, V22.4S ; +0x954, 0x101a14\nFADD V18.4S, V23.4S, V18.4S ; +0x958, 0x101a18\nSTR Q18, [X16],#0x10 ; +0x95c, 0x101a1c\nCBNZ W4, loc_101914 ; +0x960, 0x101a20\nMOV W4, W12 ; +0x964, 0x101a24\nCBZ W4, loc_101A84 ; +0x968, 0x101a28\nLDP Q18, Q19, [X17] ; +0x96c, 0x101a2c\nLDP Q20, Q21, [X17,#0x20] ; +0x970, 0x101a30\nLDR W5, [X16] ; +0x974, 0x101a34\nSUB W4, W4, #1 ; +0x978, 0x101a38\nFMUL V18.4S, V18.4S, V2.4S ; +0x97c, 0x101a3c\nFMLA V18.4S, V3.4S, V19.4S ; +0x980, 0x101a40\nFMLA V18.4S, V4.4S, V20.4S ; +0x984, 0x101a44\nLDP Q19, Q20, [X17,#0x40] ; +0x988, 0x101a48\nFMLA V18.4S, V5.4S, V21.4S ; +0x98c, 0x101a4c\nAND W5, W5, W9 ; +0x990, 0x101a50\nFMLA V18.4S, V7.4S, V19.4S ; +0x994, 0x101a54\nFMLA V18.4S, V16.4S, V20.4S ; +0x998, 0x101a58\nLDP Q19, Q20, [X17,#0x60] ; +0x99c, 0x101a5c\nADD X17, X17, #0x80 ; +0x9a0, 0x101a60\nFMLA V18.4S, V6.4S, V19.4S ; +0x9a4, 0x101a64\nFMLA V18.4S, V17.4S, V20.4S ; +0x9a8, 0x101a68\nFADDP V18.4S, V18.4S, V18.4S ; +0x9ac, 0x101a6c\nFMOV S19, W5 ; +0x9b0, 0x101a70\nFADDP S18, V18.2S ; +0x9b4, 0x101a74\nFADD S18, S18, S19 ; +0x9b8, 0x101a78\nSTR S18, [X16],#4 ; +0x9bc, 0x101a7c\nCBNZ W4, loc_101A2C ; +0x9c0, 0x101a80\nADD X1, X1, X13,LSL#2 ; +0x9c4, 0x101a84\nADD X0, X0, X14,LSL#2; jumptable 000000000010111C default case ; +0x9c8, 0x101a88\nADD W10, W10, #1 ; +0x9cc, 0x101a8c\nB loc_101100 ; +0x9d0, 0x101a90\nRET ; +0x9d4, 0x101a94", "xrefs": ["sub_101080 @ 0x1010a4"], "is_objc": false, "is_arm32": false, "is_arm64": false, "bida_info": "8.0.0 @ https://github.com/Stazzical/BromaIDA", "bindings_info": "commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings"}