{"type": "func", "start": 1057492, "end": 1058032, "name": "sub_1022D4", "pseudocode": "// \n// sub_1022D4 from 0x1022d4 to 0x1024f0 (540 bytes)\n// \n// 1 xrefs:\n// > <???> @ 0x11a100\n// \n// This function is hookable on this platform!\n// \n// Using BromaIDA 8.0.0 @ https://github.com/Stazzical/BromaIDA\n// Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings\n// \n\nfloat32x4_t *__fastcall sub_1022D4(float32x4_t *result, __int64 a2, __int64 a3, __int64 a4, const float *a5)\n{\n  __int64 v5; // x30\n  float32x4_t v6; // q0\n  float32x4_t v7; // q1\n  __int64 v8; // x8\n  long double v9; // q2\n  long double v10; // q3\n  __int64 v11; // x9\n  __int64 v12; // x5\n  long double v13; // q0\n  int8x16_t v14; // q1\n  long double v15; // q2\n  int8x16_t v16; // q3\n  long double v17; // q4\n  int v18; // w8\n  unsigned __int64 v19; // d6\n  __int64 v20; // x10\n  unsigned int v21; // w9\n  int16x8_t v22; // q16\n  float32x4_t v23; // q17\n  float32x4_t v24; // q6\n  long double v25; // q5\n  __int64 v26; // x9\n  int16x8_t v27; // q16\n  float32x4_t v28; // q7\n  float32x4_t v29; // q6\n  long double *v30; // x9\n  float32x4_t *v31; // x0\n  long double v32; // q5\n  float32x4_t v33; // q16\n  float32x4_t v34; // q17\n  float32x4_t v35; // q6\n  float32x4_t v36; // q7\n  long double v37; // q4\n  long double *v38; // x9\n  int64x2_t v39; // q3\n  long double v40; // q0\n  long double v41; // q1\n  long double v42; // q2\n  float32x4_t *v43; // x0\n  float32x4_t v44; // q5\n  float32x4_t v45; // q16\n  float32x4_t v46; // q17\n  float32x4_t v47; // q6\n  float32x4_t v48; // q7\n  int v49; // w8\n  float32x4_t v50; // q0\n  float32x4_t v51; // q1\n  __int64 v52; // x9\n  long double v53; // q2\n  long double v54; // q3\n  __int64 v55; // x10\n  __int64 v56; // x0\n  __int64 v57; // x1\n  int v58; // w8\n\n  if ( (_DWORD)a2 && ((unsigned __int8)result & 0xF) != 0 )\n  {\n    v6 = vld1q_dup_f32(a5);\n    v7 = vld1q_dup_f32((const float *)a4);\n    v8 = a3 + 16;\n    *(_QWORD *)&v9 = 0x3000000030000000LL;\n    *((_QWORD *)&v9 + 1) = 0x3000000030000000LL;\n    *(_QWORD *)&v10 = 0x3800000038000000LL;\n    *((_QWORD *)&v10 + 1) = 0x3800000038000000LL;\n    do\n    {\n      if ( ((unsigned __int8)result & 0xF) == 0 )\n        break;\n      v11 = 2LL * (unsigned int)(8 * *(_DWORD *)(a4 + 4));\n      result = (float32x4_t *)sub_102D18(\n                                *(long double *)&v6,\n                                COERCE_LONG_DOUBLE(vaddq_s32(v7, v6)),\n                                v9,\n                                v10,\n                                COERCE_LONG_DOUBLE(vmulq_f32(vcvtq_f32_u32(vshrq_n_u32(v7, 1u)), *(float32x4_t *)&v9)),\n                                *(long double *)(a3 + v11),\n                                *(long double *)(v8 + v11));\n      v5 = v12;\n      *(_QWORD *)a4 += *(_QWORD *)a5;\n    }\n    while ( (_DWORD)a2 );\n  }\n  if ( (int)a2 >> 2 )\n  {\n    result = (float32x4_t *)sub_102CA4(result, a2, a3, a4, a5, v5);\n    if ( v18 )\n    {\n      do\n      {\n        v19 = vshl_n_s32(vzip2_s32((int32x2_t)v14.n128_u64[0], (int32x2_t)vextq_s8(v14, v14, 8u).n128_u64[0]), 3u).n64_u64[0];\n        v20 = a3 + 2LL * (unsigned int)v19;\n        v21 = HIDWORD(v19);\n        v22 = *(int16x8_t *)(v20 + 16);\n        v23 = vcvtq_f32_s32(vmovl_s16(*(int16x4_t *)v20));\n        v24 = vcvtq_f32_s32(vmovl_high_s16(*(int16x8_t *)v20));\n        v25 = COERCE_LONG_DOUBLE(vmulq_f32(vcvtq_f32_u32(vshrq_n_u32(vuzp1q_s32(v14, v16), 1u)), *(float32x4_t *)&v13));\n        v26 = a3 + 2LL * v21;\n        *result = vmulq_f32(\n                    vmlaq_n_f32(\n                      v23,\n                      vsubq_f32(vcvtq_f32_s32(vmovl_s16((int16x4_t)v22.n128_u64[0])), v23),\n                      *(float *)&v25),\n                    *(float32x4_t *)&v17);\n        result[1] = vmulq_f32(\n                      vmlaq_n_f32(v24, vsubq_f32(vcvtq_f32_s32(vmovl_high_s16(v22)), v24), *(float *)&v25),\n                      *(float32x4_t *)&v17);\n        v27 = *(int16x8_t *)(v26 + 16);\n        v28 = vcvtq_f32_s32(vmovl_s16(*(int16x4_t *)v26));\n        v29 = vcvtq_f32_s32(vmovl_high_s16(*(int16x8_t *)v26));\n        v30 = (long double *)(a3\n                            + 2LL\n                            * vshl_n_s32(\n                                vzip2_s32((int32x2_t)v16.n128_u64[0], (int32x2_t)vextq_s8(v16, v16, 8u).n128_u64[0]),\n                                3u).n64_u32[0]);\n        result[2] = vmulq_f32(\n                      vmlaq_lane_f32(\n                        v28,\n                        vsubq_f32(vcvtq_f32_s32(vmovl_s16((int16x4_t)v27.n128_u64[0])), v28),\n                        *(float32x2_t *)&v25,\n                        1),\n                      *(float32x4_t *)&v17);\n        result[3] = vmulq_f32(\n                      vmlaq_lane_f32(v29, vsubq_f32(vcvtq_f32_s32(vmovl_high_s16(v27)), v29), *(float32x2_t *)&v25, 1),\n                      *(float32x4_t *)&v17);\n        v31 = (float32x4_t *)sub_102DE4(\n                               v13,\n                               COERCE_LONG_DOUBLE(vaddq_s64(v14, *(int64x2_t *)&v15)),\n                               v15,\n                               *(long double *)&v16,\n                               v17,\n                               v25,\n                               *v30,\n                               v30[1]);\n        v31[4] = vmulq_f32(vmlaq_laneq_f32(v33, v34, *(float32x4_t *)&v32, 2), *(float32x4_t *)&v37);\n        v31[5] = vmulq_f32(vmlaq_laneq_f32(v35, v36, *(float32x4_t *)&v32, 2), *(float32x4_t *)&v37);\n        v43 = (float32x4_t *)sub_102DE4(\n                               v40,\n                               v41,\n                               v42,\n                               COERCE_LONG_DOUBLE(vaddq_s64(v39, *(int64x2_t *)&v42)),\n                               v37,\n                               v32,\n                               *v38,\n                               v38[1]);\n        v43[6] = vmulq_f32(vmlaq_laneq_f32(v45, v46, v44, 3), *(float32x4_t *)&v17);\n        v43[7] = vmulq_f32(vmlaq_laneq_f32(v47, v48, v44, 3), *(float32x4_t *)&v17);\n        result = v43 + 8;\n      }\n      while ( v49 );\n    }\n    *(_QWORD *)a4 = v14.n128_u64[0];\n  }\n  if ( (a2 & 3) != 0 )\n  {\n    v50 = vld1q_dup_f32(a5);\n    v51 = vld1q_dup_f32((const float *)a4);\n    v52 = a3 + 16;\n    *(_QWORD *)&v53 = 0x3000000030000000LL;\n    *((_QWORD *)&v53 + 1) = 0x3000000030000000LL;\n    *(_QWORD *)&v54 = 0x3800000038000000LL;\n    *((_QWORD *)&v54 + 1) = 0x3800000038000000LL;\n    do\n    {\n      v55 = 2LL * (unsigned int)(8 * *(_DWORD *)(a4 + 4));\n      v56 = sub_102D18(\n              *(long double *)&v50,\n              COERCE_LONG_DOUBLE(vaddq_s32(v51, v50)),\n              v53,\n              v54,\n              COERCE_LONG_DOUBLE(vmulq_f32(vcvtq_f32_u32(vshrq_n_u32(v51, 1u)), *(float32x4_t *)&v53)),\n              *(long double *)(a3 + v55),\n              *(long double *)(v52 + v55));\n      result = (float32x4_t *)sub_102E10(v56, v57);\n    }\n    while ( v58 );\n  }\n  return result;\n}", "assembly": "; \n; sub_1022D4 from 0x1022d4 to 0x1024f0 (540 bytes)\n; \n; 1 xrefs:\n; > <???> @ 0x11a100\n; \n; This function is hookable on this platform!\n; \n; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA\n; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings\n; \n\nCBZ             W1, loc_102348                                         ; +0x0, 0x1022d4\nAND             X8, X0, #0xF                                           ; +0x4, 0x1022d8\nCBZ             X8, loc_102348                                         ; +0x8, 0x1022dc\nLD1R            {V0.4S}, [X4]                                          ; +0xc, 0x1022e0\nLD1R            {V1.4S}, [X3]                                          ; +0x10, 0x1022e4\nADD             X8, X2, #0x10                                          ; +0x14, 0x1022e8\nMOVI            V2.4S, #0x30,LSL#24 ; '0'                              ; +0x18, 0x1022ec\nMOVI            V3.4S, #0x38,LSL#24 ; '8'                              ; +0x1c, 0x1022f0\nCBZ             W1, loc_102348                                         ; +0x20, 0x1022f4\nAND             X9, X0, #0xF                                           ; +0x24, 0x1022f8\nCBZ             X9, loc_102348                                         ; +0x28, 0x1022fc\nLDR             W9, [X3,#4]                                            ; +0x2c, 0x102300\nUSHR            V4.4S, V1.4S, #1                                       ; +0x30, 0x102304\nUCVTF           V4.4S, V4.4S                                           ; +0x34, 0x102308\nFMUL            V4.4S, V4.4S, V2.4S                                    ; +0x38, 0x10230c\nLSL             W9, W9, #3                                             ; +0x3c, 0x102310\nLSL             X9, X9, #1                                             ; +0x40, 0x102314\nLDR             Q5, [X2,X9]                                            ; +0x44, 0x102318\nLDR             Q6, [X8,X9]                                            ; +0x48, 0x10231c\nADD             V1.4S, V1.4S, V0.4S                                    ; +0x4c, 0x102320\nSUB             W1, W1, #1                                             ; +0x50, 0x102324\nMOV             X5, X30                                                ; +0x54, 0x102328\nBL              sub_102D18                                             ; +0x58, 0x10232c\nMOV             X30, X5                                                ; +0x5c, 0x102330\nLDR             X9, [X4]                                               ; +0x60, 0x102334\nLDR             X10, [X3]                                              ; +0x64, 0x102338\nADD             X9, X10, X9                                            ; +0x68, 0x10233c\nSTR             X9, [X3]                                               ; +0x6c, 0x102340\nCBNZ            W1, loc_1022F8                                         ; +0x70, 0x102344\nASR             W8, W1, #2                                             ; +0x74, 0x102348\nCBZ             W8, loc_102488                                         ; +0x78, 0x10234c\nMOV             X5, X30                                                ; +0x7c, 0x102350\nBL              sub_102CA4                                             ; +0x80, 0x102354\nMOV             X30, X5                                                ; +0x84, 0x102358\nCBZ             W8, loc_102484                                         ; +0x88, 0x10235c\nEXT             V6.16B, V1.16B, V1.16B, #8                             ; +0x8c, 0x102360\nZIP2            V6.2S, V1.2S, V6.2S                                    ; +0x90, 0x102364\nSHL             V6.2S, V6.2S, #3                                       ; +0x94, 0x102368\nFMOV            W10, S6                                                ; +0x98, 0x10236c\nADD             X10, X2, W10,UXTW#1                                    ; +0x9c, 0x102370\nUMOV            W9, V6.S[1]                                            ; +0xa0, 0x102374\nLDP             Q6, Q16, [X10]                                         ; +0xa4, 0x102378\nUZP1            V5.4S, V1.4S, V3.4S                                    ; +0xa8, 0x10237c\nUSHR            V5.4S, V5.4S, #1                                       ; +0xac, 0x102380\nUCVTF           V5.4S, V5.4S                                           ; +0xb0, 0x102384\nSSHLL           V17.4S, V6.4H, #0                                      ; +0xb4, 0x102388\nSSHLL2          V6.4S, V6.8H, #0                                       ; +0xb8, 0x10238c\nSSHLL           V18.4S, V16.4H, #0                                     ; +0xbc, 0x102390\nSSHLL2          V16.4S, V16.8H, #0                                     ; +0xc0, 0x102394\nSCVTF           V17.4S, V17.4S                                         ; +0xc4, 0x102398\nSCVTF           V6.4S, V6.4S                                           ; +0xc8, 0x10239c\nSCVTF           V18.4S, V18.4S                                         ; +0xcc, 0x1023a0\nSCVTF           V16.4S, V16.4S                                         ; +0xd0, 0x1023a4\nFMUL            V5.4S, V5.4S, V0.4S                                    ; +0xd4, 0x1023a8\nFSUB            V18.4S, V18.4S, V17.4S                                 ; +0xd8, 0x1023ac\nFSUB            V16.4S, V16.4S, V6.4S                                  ; +0xdc, 0x1023b0\nFMLA            V17.4S, V18.4S, V5.S[0]                                ; +0xe0, 0x1023b4\nFMLA            V6.4S, V16.4S, V5.S[0]                                 ; +0xe4, 0x1023b8\nFMUL            V16.4S, V17.4S, V4.4S                                  ; +0xe8, 0x1023bc\nFMUL            V6.4S, V6.4S, V4.4S                                    ; +0xec, 0x1023c0\nADD             X9, X2, W9,UXTW#1                                      ; +0xf0, 0x1023c4\nSTP             Q16, Q6, [X0]                                          ; +0xf4, 0x1023c8\nLDP             Q6, Q16, [X9]                                          ; +0xf8, 0x1023cc\nEXT             V7.16B, V3.16B, V3.16B, #8                             ; +0xfc, 0x1023d0\nZIP2            V7.2S, V3.2S, V7.2S                                    ; +0x100, 0x1023d4\nSHL             V7.2S, V7.2S, #3                                       ; +0x104, 0x1023d8\nUMOV            W10, V7.S[1]                                           ; +0x108, 0x1023dc\nFMOV            W9, S7                                                 ; +0x10c, 0x1023e0\nSSHLL           V7.4S, V6.4H, #0                                       ; +0x110, 0x1023e4\nSSHLL2          V6.4S, V6.8H, #0                                       ; +0x114, 0x1023e8\nSSHLL           V17.4S, V16.4H, #0                                     ; +0x118, 0x1023ec\nSSHLL2          V16.4S, V16.8H, #0                                     ; +0x11c, 0x1023f0\nSCVTF           V7.4S, V7.4S                                           ; +0x120, 0x1023f4\nSCVTF           V6.4S, V6.4S                                           ; +0x124, 0x1023f8\nSCVTF           V17.4S, V17.4S                                         ; +0x128, 0x1023fc\nSCVTF           V16.4S, V16.4S                                         ; +0x12c, 0x102400\nFSUB            V17.4S, V17.4S, V7.4S                                  ; +0x130, 0x102404\nFSUB            V16.4S, V16.4S, V6.4S                                  ; +0x134, 0x102408\nFMLA            V7.4S, V17.4S, V5.S[1]                                 ; +0x138, 0x10240c\nFMLA            V6.4S, V16.4S, V5.S[1]                                 ; +0x13c, 0x102410\nFMUL            V7.4S, V7.4S, V4.4S                                    ; +0x140, 0x102414\nFMUL            V6.4S, V6.4S, V4.4S                                    ; +0x144, 0x102418\nADD             X9, X2, W9,UXTW#1                                      ; +0x148, 0x10241c\nSTP             Q7, Q6, [X0,#0x20]                                     ; +0x14c, 0x102420\nLDP             Q6, Q7, [X9]                                           ; +0x150, 0x102424\nADD             X9, X2, W10,UXTW#1                                     ; +0x154, 0x102428\nSUB             W8, W8, #1                                             ; +0x158, 0x10242c\nADD             V1.2D, V1.2D, V2.2D                                    ; +0x15c, 0x102430\nMOV             X5, X30                                                ; +0x160, 0x102434\nBL              sub_102DE4                                             ; +0x164, 0x102438\nMOV             X30, X5                                                ; +0x168, 0x10243c\nFMLA            V16.4S, V17.4S, V5.S[2]                                ; +0x16c, 0x102440\nFMLA            V6.4S, V7.4S, V5.S[2]                                  ; +0x170, 0x102444\nFMUL            V7.4S, V16.4S, V4.4S                                   ; +0x174, 0x102448\nFMUL            V6.4S, V6.4S, V4.4S                                    ; +0x178, 0x10244c\nSTP             Q7, Q6, [X0,#0x40]                                     ; +0x17c, 0x102450\nLDP             Q6, Q7, [X9]                                           ; +0x180, 0x102454\nADD             V3.2D, V3.2D, V2.2D                                    ; +0x184, 0x102458\nMOV             X5, X30                                                ; +0x188, 0x10245c\nBL              sub_102DE4                                             ; +0x18c, 0x102460\nMOV             X30, X5                                                ; +0x190, 0x102464\nFMLA            V16.4S, V17.4S, V5.S[3]                                ; +0x194, 0x102468\nFMLA            V6.4S, V7.4S, V5.S[3]                                  ; +0x198, 0x10246c\nFMUL            V5.4S, V16.4S, V4.4S                                   ; +0x19c, 0x102470\nFMUL            V6.4S, V6.4S, V4.4S                                    ; +0x1a0, 0x102474\nSTP             Q5, Q6, [X0,#0x60]                                     ; +0x1a4, 0x102478\nADD             X0, X0, #0x80                                          ; +0x1a8, 0x10247c\nCBNZ            W8, loc_102360                                         ; +0x1ac, 0x102480\nSTR             D1, [X3]                                               ; +0x1b0, 0x102484\nANDS            W8, W1, #3                                             ; +0x1b4, 0x102488\nB.EQ            locret_1024EC                                          ; +0x1b8, 0x10248c\nLD1R            {V0.4S}, [X4]                                          ; +0x1bc, 0x102490\nLD1R            {V1.4S}, [X3]                                          ; +0x1c0, 0x102494\nADD             X9, X2, #0x10                                          ; +0x1c4, 0x102498\nMOVI            V2.4S, #0x30,LSL#24 ; '0'                              ; +0x1c8, 0x10249c\nMOVI            V3.4S, #0x38,LSL#24 ; '8'                              ; +0x1cc, 0x1024a0\nCBZ             W8, locret_1024EC                                      ; +0x1d0, 0x1024a4\nLDR             W10, [X3,#4]                                           ; +0x1d4, 0x1024a8\nUSHR            V4.4S, V1.4S, #1                                       ; +0x1d8, 0x1024ac\nUCVTF           V4.4S, V4.4S                                           ; +0x1dc, 0x1024b0\nFMUL            V4.4S, V4.4S, V2.4S                                    ; +0x1e0, 0x1024b4\nLSL             W10, W10, #3                                           ; +0x1e4, 0x1024b8\nLSL             X10, X10, #1                                           ; +0x1e8, 0x1024bc\nLDR             Q5, [X2,X10]                                           ; +0x1ec, 0x1024c0\nLDR             Q6, [X9,X10]                                           ; +0x1f0, 0x1024c4\nADD             V1.4S, V1.4S, V0.4S                                    ; +0x1f4, 0x1024c8\nSUB             W8, W8, #1                                             ; +0x1f8, 0x1024cc\nMOV             X1, X30                                                ; +0x1fc, 0x1024d0\nBL              sub_102D18                                             ; +0x200, 0x1024d4\nMOV             X30, X1                                                ; +0x204, 0x1024d8\nMOV             X1, X30                                                ; +0x208, 0x1024dc\nBL              sub_102E10                                             ; +0x20c, 0x1024e0\nMOV             X30, X1                                                ; +0x210, 0x1024e4\nCBNZ            W8, loc_1024A8                                         ; +0x214, 0x1024e8\nRET                                                                    ; +0x218, 0x1024ec", "xrefs": ["<???> @ 0x11a100"], "is_objc": false, "is_arm32": false, "is_arm64": false, "bida_info": "8.0.0 @ https://github.com/Stazzical/BromaIDA", "bindings_info": "commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings"}