{"type": "func", "start": 1059548, "end": 1060004, "name": "sub_102ADC", "pseudocode": "// \n// sub_102ADC from 0x102adc to 0x102ca4 (456 bytes)\n// \n// 1 xrefs:\n// > <???> @ 0x11a128\n// \n// This function is hookable on this platform!\n// \n// Using BromaIDA 8.0.0 @ https://github.com/Stazzical/BromaIDA\n// Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings\n// \n\n__int64 __fastcall sub_102ADC(__int64 result, __int64 a2, __int64 a3, __int64 a4, const float *a5)\n{\n  __int64 v5; // x30\n  float32x4_t v6; // q0\n  float32x4_t v7; // q1\n  float32x4_t v8; // q2\n  float32x4_t v9; // q3\n  float32x4_t *v10; // x8\n  float32x4_t v11; // q5\n  int v12; // w8\n  int8x16_t v13; // q0\n  int64x2_t v14; // q1\n  int8x16_t v15; // q2\n  float32x4_t v16; // q3\n  unsigned __int64 v17; // d5\n  float32x4_t *v18; // x10\n  float32x4_t v19; // q4\n  float32x4_t v20; // q7\n  float32x4_t *v21; // x9\n  float32x4_t v22; // q7\n  float32x4_t v23; // q17\n  unsigned __int64 v24; // d6\n  float32x4_t *v25; // x10\n  float32x4_t *v26; // x9\n  float32x4_t v27; // q6\n  float32x4_t v28; // q6\n  int v29; // w8\n  float32x4_t v30; // q0\n  float32x4_t v31; // q1\n  float32x4_t v32; // q2\n  float32x4_t v33; // q3\n  float32x4_t *v34; // x9\n  float32x4_t v35; // q5\n\n  if ( (_DWORD)a2 && (result & 0xF) != 0 )\n  {\n    v6 = vld1q_dup_f32(a5);\n    v7 = vld1q_dup_f32((const float *)a4);\n    v8.n128_u64[0] = 0x3000000030000000LL;\n    v8.n128_u64[1] = 0x3000000030000000LL;\n    do\n    {\n      if ( (result & 0xF) == 0 )\n        break;\n      v9 = vmulq_f32(vcvtq_f32_u32(vshrq_n_u32(v7, 1u)), v8);\n      v10 = (float32x4_t *)(a3 + 4LL * (unsigned int)(8 * *(_DWORD *)(a4 + 4)));\n      v7 = vaddq_s32(v7, v6);\n      a2 = (unsigned int)(a2 - 1);\n      v11 = vmlaq_f32(v10[1], v9, vsubq_f32(v10[3], v10[1]));\n      *(float32x4_t *)result = vmlaq_f32(*v10, v9, vsubq_f32(v10[2], *v10));\n      *(float32x4_t *)(result + 16) = v11;\n      result += 32;\n      *(_QWORD *)a4 += *(_QWORD *)a5;\n    }\n    while ( (_DWORD)a2 );\n  }\n  if ( (int)a2 >> 2 )\n  {\n    for ( result = sub_102CE0(result, a2, a3, a4, a5, v5); v12; result += 128 )\n    {\n      v17 = vshl_n_s32(vzip2_s32((int32x2_t)v13.n128_u64[0], (int32x2_t)vextq_s8(v13, v13, 8u).n128_u64[0]), 3u).n64_u64[0];\n      v18 = (float32x4_t *)(a3 + 4LL * (unsigned int)v17);\n      v19 = vmulq_f32(vcvtq_f32_u32(vshrq_n_u32(vuzp1q_s32(v13, v15), 1u)), v16);\n      v20 = vmlaq_n_f32(v18[1], vsubq_f32(v18[3], v18[1]), v19.n128_f32[0]);\n      v21 = (float32x4_t *)(a3 + 4LL * HIDWORD(v17));\n      *(float32x4_t *)result = vmlaq_n_f32(*v18, vsubq_f32(v18[2], *v18), v19.n128_f32[0]);\n      *(float32x4_t *)(result + 16) = v20;\n      v22 = v21[1];\n      v23 = v21[3];\n      v24 = vshl_n_s32(vzip2_s32((int32x2_t)v15.n128_u64[0], (int32x2_t)vextq_s8(v15, v15, 8u).n128_u64[0]), 3u).n64_u64[0];\n      v25 = (float32x4_t *)(a3 + 4LL * (unsigned int)v24);\n      *(float32x4_t *)(result + 32) = vmlaq_lane_f32(*v21, vsubq_f32(v21[2], *v21), (float32x2_t)v19.n128_u64[0], 1);\n      *(float32x4_t *)(result + 48) = vmlaq_lane_f32(v22, vsubq_f32(v23, v22), (float32x2_t)v19.n128_u64[0], 1);\n      v26 = (float32x4_t *)(a3 + 4LL * HIDWORD(v24));\n      --v12;\n      v13 = vaddq_s64(v13, v14);\n      v27 = vmlaq_laneq_f32(v25[1], vsubq_f32(v25[3], v25[1]), v19, 2);\n      *(float32x4_t *)(result + 64) = vmlaq_laneq_f32(*v25, vsubq_f32(v25[2], *v25), v19, 2);\n      *(float32x4_t *)(result + 80) = v27;\n      v15 = vaddq_s64(v15, v14);\n      v28 = vmlaq_laneq_f32(v26[1], vsubq_f32(v26[3], v26[1]), v19, 3);\n      *(float32x4_t *)(result + 96) = vmlaq_laneq_f32(*v26, vsubq_f32(v26[2], *v26), v19, 3);\n      *(float32x4_t *)(result + 112) = v28;\n    }\n    *(_QWORD *)a4 = v13.n128_u64[0];\n  }\n  v29 = a2 & 3;\n  if ( (a2 & 3) != 0 )\n  {\n    v30 = vld1q_dup_f32(a5);\n    v31 = vld1q_dup_f32((const float *)a4);\n    v32.n128_u64[0] = 0x3000000030000000LL;\n    v32.n128_u64[1] = 0x3000000030000000LL;\n    do\n    {\n      v33 = vmulq_f32(vcvtq_f32_u32(vshrq_n_u32(v31, 1u)), v32);\n      v34 = (float32x4_t *)(a3 + 4LL * (unsigned int)(8 * *(_DWORD *)(a4 + 4)));\n      v31 = vaddq_s32(v31, v30);\n      --v29;\n      v35 = vmlaq_f32(v34[1], v33, vsubq_f32(v34[3], v34[1]));\n      *(float32x4_t *)result = vmlaq_f32(*v34, v33, vsubq_f32(v34[2], *v34));\n      *(float32x4_t *)(result + 16) = v35;\n      result += 32;\n      *(_QWORD *)a4 += *(_QWORD *)a5;\n    }\n    while ( v29 );\n  }\n  return result;\n}", "assembly": "; \n; sub_102ADC from 0x102adc to 0x102ca4 (456 bytes)\n; \n; 1 xrefs:\n; > <???> @ 0x11a128\n; \n; This function is hookable on this platform!\n; \n; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA\n; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings\n; \n\nCBZ             W1, loc_102B50                                         ; +0x0, 0x102adc\nAND             X8, X0, #0xF                                           ; +0x4, 0x102ae0\nCBZ             X8, loc_102B50                                         ; +0x8, 0x102ae4\nLD1R            {V0.4S}, [X4]                                          ; +0xc, 0x102ae8\nLD1R            {V1.4S}, [X3]                                          ; +0x10, 0x102aec\nMOVI            V2.4S, #0x30,LSL#24 ; '0'                              ; +0x14, 0x102af0\nCBZ             W1, loc_102B50                                         ; +0x18, 0x102af4\nAND             X8, X0, #0xF                                           ; +0x1c, 0x102af8\nCBZ             X8, loc_102B50                                         ; +0x20, 0x102afc\nLDR             W8, [X3,#4]                                            ; +0x24, 0x102b00\nUSHR            V3.4S, V1.4S, #1                                       ; +0x28, 0x102b04\nUCVTF           V3.4S, V3.4S                                           ; +0x2c, 0x102b08\nFMUL            V3.4S, V3.4S, V2.4S                                    ; +0x30, 0x102b0c\nLSL             W8, W8, #3                                             ; +0x34, 0x102b10\nADD             X8, X2, W8,UXTW#2                                      ; +0x38, 0x102b14\nLDP             Q4, Q5, [X8]                                           ; +0x3c, 0x102b18\nLDP             Q6, Q7, [X8,#0x20]                                     ; +0x40, 0x102b1c\nADD             V1.4S, V1.4S, V0.4S                                    ; +0x44, 0x102b20\nSUB             W1, W1, #1                                             ; +0x48, 0x102b24\nFSUB            V6.4S, V6.4S, V4.4S                                    ; +0x4c, 0x102b28\nFSUB            V7.4S, V7.4S, V5.4S                                    ; +0x50, 0x102b2c\nFMLA            V4.4S, V3.4S, V6.4S                                    ; +0x54, 0x102b30\nFMLA            V5.4S, V3.4S, V7.4S                                    ; +0x58, 0x102b34\nSTP             Q4, Q5, [X0],#0x20                                     ; +0x5c, 0x102b38\nLDR             X8, [X4]                                               ; +0x60, 0x102b3c\nLDR             X9, [X3]                                               ; +0x64, 0x102b40\nADD             X8, X9, X8                                             ; +0x68, 0x102b44\nSTR             X8, [X3]                                               ; +0x6c, 0x102b48\nCBNZ            W1, loc_102AF8                                         ; +0x70, 0x102b4c\nASR             W8, W1, #2                                             ; +0x74, 0x102b50\nCBZ             W8, loc_102C38                                         ; +0x78, 0x102b54\nMOV             X5, X30                                                ; +0x7c, 0x102b58\nBL              sub_102CE0                                             ; +0x80, 0x102b5c\nMOV             X30, X5                                                ; +0x84, 0x102b60\nCBZ             W8, loc_102C34                                         ; +0x88, 0x102b64\nEXT             V5.16B, V0.16B, V0.16B, #8                             ; +0x8c, 0x102b68\nZIP2            V5.2S, V0.2S, V5.2S                                    ; +0x90, 0x102b6c\nSHL             V5.2S, V5.2S, #3                                       ; +0x94, 0x102b70\nFMOV            W10, S5                                                ; +0x98, 0x102b74\nADD             X10, X2, W10,UXTW#2                                    ; +0x9c, 0x102b78\nUMOV            W9, V5.S[1]                                            ; +0xa0, 0x102b7c\nLDP             Q5, Q7, [X10]                                          ; +0xa4, 0x102b80\nLDP             Q16, Q17, [X10,#0x20]                                  ; +0xa8, 0x102b84\nUZP1            V4.4S, V0.4S, V2.4S                                    ; +0xac, 0x102b88\nUSHR            V4.4S, V4.4S, #1                                       ; +0xb0, 0x102b8c\nUCVTF           V4.4S, V4.4S                                           ; +0xb4, 0x102b90\nFMUL            V4.4S, V4.4S, V3.4S                                    ; +0xb8, 0x102b94\nFSUB            V16.4S, V16.4S, V5.4S                                  ; +0xbc, 0x102b98\nFSUB            V17.4S, V17.4S, V7.4S                                  ; +0xc0, 0x102b9c\nFMLA            V5.4S, V16.4S, V4.S[0]                                 ; +0xc4, 0x102ba0\nFMLA            V7.4S, V17.4S, V4.S[0]                                 ; +0xc8, 0x102ba4\nADD             X9, X2, W9,UXTW#2                                      ; +0xcc, 0x102ba8\nSTP             Q5, Q7, [X0]                                           ; +0xd0, 0x102bac\nLDP             Q5, Q7, [X9]                                           ; +0xd4, 0x102bb0\nLDP             Q16, Q17, [X9,#0x20]                                   ; +0xd8, 0x102bb4\nEXT             V6.16B, V2.16B, V2.16B, #8                             ; +0xdc, 0x102bb8\nZIP2            V6.2S, V2.2S, V6.2S                                    ; +0xe0, 0x102bbc\nSHL             V6.2S, V6.2S, #3                                       ; +0xe4, 0x102bc0\nUMOV            W9, V6.S[1]                                            ; +0xe8, 0x102bc4\nFMOV            W10, S6                                                ; +0xec, 0x102bc8\nFSUB            V6.4S, V16.4S, V5.4S                                   ; +0xf0, 0x102bcc\nFSUB            V16.4S, V17.4S, V7.4S                                  ; +0xf4, 0x102bd0\nFMLA            V5.4S, V6.4S, V4.S[1]                                  ; +0xf8, 0x102bd4\nFMLA            V7.4S, V16.4S, V4.S[1]                                 ; +0xfc, 0x102bd8\nADD             X10, X2, W10,UXTW#2                                    ; +0x100, 0x102bdc\nSTP             Q5, Q7, [X0,#0x20]                                     ; +0x104, 0x102be0\nLDP             Q5, Q6, [X10]                                          ; +0x108, 0x102be4\nLDP             Q7, Q16, [X10,#0x20]                                   ; +0x10c, 0x102be8\nADD             X9, X2, W9,UXTW#2                                      ; +0x110, 0x102bec\nSUB             W8, W8, #1                                             ; +0x114, 0x102bf0\nADD             V0.2D, V0.2D, V1.2D                                    ; +0x118, 0x102bf4\nFSUB            V7.4S, V7.4S, V5.4S                                    ; +0x11c, 0x102bf8\nFSUB            V16.4S, V16.4S, V6.4S                                  ; +0x120, 0x102bfc\nFMLA            V5.4S, V7.4S, V4.S[2]                                  ; +0x124, 0x102c00\nFMLA            V6.4S, V16.4S, V4.S[2]                                 ; +0x128, 0x102c04\nSTP             Q5, Q6, [X0,#0x40]                                     ; +0x12c, 0x102c08\nLDP             Q5, Q6, [X9]                                           ; +0x130, 0x102c0c\nLDP             Q7, Q16, [X9,#0x20]                                    ; +0x134, 0x102c10\nADD             V2.2D, V2.2D, V1.2D                                    ; +0x138, 0x102c14\nFSUB            V7.4S, V7.4S, V5.4S                                    ; +0x13c, 0x102c18\nFSUB            V16.4S, V16.4S, V6.4S                                  ; +0x140, 0x102c1c\nFMLA            V5.4S, V7.4S, V4.S[3]                                  ; +0x144, 0x102c20\nFMLA            V6.4S, V16.4S, V4.S[3]                                 ; +0x148, 0x102c24\nSTP             Q5, Q6, [X0,#0x60]                                     ; +0x14c, 0x102c28\nADD             X0, X0, #0x80                                          ; +0x150, 0x102c2c\nCBNZ            W8, loc_102B68                                         ; +0x154, 0x102c30\nSTR             D0, [X3]                                               ; +0x158, 0x102c34\nANDS            W8, W1, #3                                             ; +0x15c, 0x102c38\nB.EQ            locret_102CA0                                          ; +0x160, 0x102c3c\nLD1R            {V0.4S}, [X4]                                          ; +0x164, 0x102c40\nLD1R            {V1.4S}, [X3]                                          ; +0x168, 0x102c44\nMOVI            V2.4S, #0x30,LSL#24 ; '0'                              ; +0x16c, 0x102c48\nCBZ             W8, locret_102CA0                                      ; +0x170, 0x102c4c\nLDR             W9, [X3,#4]                                            ; +0x174, 0x102c50\nUSHR            V3.4S, V1.4S, #1                                       ; +0x178, 0x102c54\nUCVTF           V3.4S, V3.4S                                           ; +0x17c, 0x102c58\nFMUL            V3.4S, V3.4S, V2.4S                                    ; +0x180, 0x102c5c\nLSL             W9, W9, #3                                             ; +0x184, 0x102c60\nADD             X9, X2, W9,UXTW#2                                      ; +0x188, 0x102c64\nLDP             Q4, Q5, [X9]                                           ; +0x18c, 0x102c68\nLDP             Q6, Q7, [X9,#0x20]                                     ; +0x190, 0x102c6c\nADD             V1.4S, V1.4S, V0.4S                                    ; +0x194, 0x102c70\nSUB             W8, W8, #1                                             ; +0x198, 0x102c74\nFSUB            V6.4S, V6.4S, V4.4S                                    ; +0x19c, 0x102c78\nFSUB            V7.4S, V7.4S, V5.4S                                    ; +0x1a0, 0x102c7c\nFMLA            V4.4S, V3.4S, V6.4S                                    ; +0x1a4, 0x102c80\nFMLA            V5.4S, V3.4S, V7.4S                                    ; +0x1a8, 0x102c84\nSTP             Q4, Q5, [X0],#0x20                                     ; +0x1ac, 0x102c88\nLDR             X9, [X4]                                               ; +0x1b0, 0x102c8c\nLDR             X10, [X3]                                              ; +0x1b4, 0x102c90\nADD             X9, X10, X9                                            ; +0x1b8, 0x102c94\nSTR             X9, [X3]                                               ; +0x1bc, 0x102c98\nCBNZ            W8, loc_102C50                                         ; +0x1c0, 0x102c9c\nRET                                                                    ; +0x1c4, 0x102ca0", "xrefs": ["<???> @ 0x11a128"], "is_objc": false, "is_arm32": false, "is_arm64": false, "bida_info": "8.0.0 @ https://github.com/Stazzical/BromaIDA", "bindings_info": "commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings"}