{"type": "func", "start": 1060388, "end": 1060944, "name": "sub_102E24", "pseudocode": "// \n// sub_102E24 from 0x102e24 to 0x103050 (556 bytes)\n// \n// 1 xrefs:\n// > sub_87AB0 @ 0x87ae8\n// \n// This function is hookable on this platform!\n// \n// Using BromaIDA 8.0.0 @ https://github.com/Stazzical/BromaIDA\n// Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings\n// \n\n__int64 __fastcall sub_102E24(__int64 a1)\n{\n  int v2; // w8\n  int v3; // w14\n  float32x4_t *v4; // x11\n  int v5; // w9\n  int v6; // w10\n  int32x4_t *v7; // x12\n  int32x4_t *v8; // x13\n  int i; // w14\n  int32x4_t v10; // q1\n  int32x4_t v11; // q2\n  int32x4_t v12; // q3\n  int32x4_t v13; // q4\n  float32x4_t v14; // q7\n  float32x4_t v15; // q1\n  __int64 v16; // x11\n  __int64 v17; // x10\n  int32x2_t v18; // d2\n  float32x2_t v19; // d1\n  float32x2_t v20; // d2\n  float32x2_t v21; // d3\n  __int64 v22; // x1\n  __int64 v23; // x8\n  __int64 v24; // x10\n  int v25; // w9\n  __int64 v26; // x8\n  int v27; // w9\n  __int64 v28; // x10\n  float *v29; // x12\n  __int64 v30; // x11\n  __int64 result; // x0\n  int32x2_t v32; // d0\n  float32x4_t *v33; // x12\n  __int64 v34; // x13\n  float32x4_t *v35; // x9\n  int v36; // w8\n  float32x4_t *v37; // x10\n  int32x4_t v38; // q0\n  __int64 v39; // x11\n  float32x4_t v40; // q1\n  float32x4_t v41; // q3\n  float32x4_t v42; // q1\n\n  v2 = 0;\n  while ( v2 < *(_DWORD *)(a1 + 20) )\n  {\n    v3 = *(_DWORD *)(a1 + 16);\n    v4 = *(float32x4_t **)(a1 + 120);\n    v5 = (v3 + 1) * ((*(_DWORD *)(a1 + 84) + v2 + *(_DWORD *)(a1 + 24)) % *(_DWORD *)(a1 + 32));\n    v6 = (v3 + 1) * v2;\n    v7 = (int32x4_t *)(*(_QWORD *)(a1 + 112) + 8LL * v6);\n    v8 = (int32x4_t *)(*(_QWORD *)(a1 + 96) + 8LL * v5);\n    for ( i = v3 >> 2; i; v4 += 2 )\n    {\n      v10 = *v8;\n      v11 = v8[1];\n      v8 += 2;\n      v12 = *v7;\n      v13 = v7[1];\n      v7 += 2;\n      --i;\n      v14 = vmlaq_f32(\n              vmulq_f32(v12, vtrn1q_s32(v10, v10)),\n              vrev64q_s32(v12),\n              vmulq_f32(vtrn2q_s32(v10, v10), (float32x4_t)xmmword_2F660));\n      v15 = vaddq_f32(\n              vmlaq_f32(\n                vmulq_f32(v13, vtrn1q_s32(v11, v11)),\n                vrev64q_s32(v13),\n                vmulq_f32(vtrn2q_s32(v11, v11), (float32x4_t)xmmword_2F660)),\n              v4[1]);\n      *v4 = vaddq_f32(v14, *v4);\n      v4[1] = v15;\n    }\n    v16 = *(int *)(a1 + 16);\n    ++v2;\n    v17 = *(_QWORD *)(a1 + 112) + 8LL * ((int)v16 + v6);\n    v18.n64_u64[0] = *(unsigned __int64 *)(*(_QWORD *)(a1 + 96) + 8LL * ((int)v16 + v5));\n    v19.n64_u64[0] = vmul_f32(v18, vld1_dup_f32((const float *)v17)).n64_u64[0];\n    v20.n64_u64[0] = vmul_n_f32(vrev64_s32(v18), *(float *)(v17 + 4)).n64_u64[0];\n    v21.n64_u32[0] = vsub_f32(v19, v20).n64_u32[0];\n    v21.n64_u32[1] = vadd_f32(v19, v20).n64_u32[1];\n    *(float32x2_t *)(*(_QWORD *)(a1 + 120) + 8 * v16) = vadd_f32(v21, *(float32x2_t *)(*(_QWORD *)(a1 + 120) + 8 * v16));\n  }\n  v22 = *(_QWORD *)(a1 + 120);\n  v23 = *(int *)(a1 + 36);\n  v24 = v22 + 8 * v23;\n  v25 = *(int *)(a1 + 16) >> 2;\n  *(float *)(v24 - 12) = -*(float *)(v22 + 20);\n  v26 = 8 * v23 - 28;\n  v27 = v25 - 1;\n  *(float *)(v24 - 20) = -*(float *)(v22 + 28);\n  v28 = 36;\n  while ( 1 )\n  {\n    v29 = (float *)(v22 + v28);\n    v30 = v22 + v26;\n    *(float *)(v22 + v26) = -*(float *)(v22 + v28);\n    if ( !v27 )\n      break;\n    v26 -= 32;\n    v28 += 32;\n    --v27;\n    *(float *)(v30 - 8) = -v29[2];\n    *(float *)(v30 - 16) = -v29[4];\n    *(float *)(v30 - 24) = -v29[6];\n  }\n  result = sub_7259C(*(_QWORD *)(a1 + 72), v22, *(float **)(a1 + 128), 0, 1);\n  if ( !(_DWORD)result )\n  {\n    v33 = *(float32x4_t **)(a1 + 64);\n    v34 = *(int *)(a1 + 16);\n    v35 = *(float32x4_t **)(a1 + 128);\n    v32.n64_f32[0] = 1.0 / (float)*(int *)(a1 + 36);\n    v36 = 0;\n    v37 = (float32x4_t *)(*(_QWORD *)(a1 + 56) + 4LL * *(int *)(a1 + 92));\n    v38 = vdupq_lane_s32(v32, 0);\n    v39 = 4 * v34;\n    while ( v36 < (int)v34 )\n    {\n      v40 = *v35;\n      v41 = *(float32x4_t *)((char *)v35++ + v39);\n      v36 += 4;\n      v42 = vmulq_f32(vaddq_f32(*v33, v40), v38);\n      *v33 = v41;\n      *v37++ = v42;\n      LODWORD(v34) = *(_DWORD *)(a1 + 16);\n      ++v33;\n    }\n    return 0;\n  }\n  return result;\n}", "assembly": "; \n; sub_102E24 from 0x102e24 to 0x103050 (556 bytes)\n; \n; 1 xrefs:\n; > sub_87AB0 @ 0x87ae8\n; \n; This function is hookable on this platform!\n; \n; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA\n; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings\n; \n\nSTR             X19, [SP,#-0x10+var_10]!                               ; +0x0, 0x102e24\nADRP            X8, #xmmword_2F660@PAGE                                ; +0x4, 0x102e28\nLDR             Q0, [X8,#xmmword_2F660@PAGEOFF]                        ; +0x8, 0x102e2c\nMOV             X19, X0                                                ; +0xc, 0x102e30\nMOV             W8, WZR                                                ; +0x10, 0x102e34\nSTP             X29, X30, [SP,#0x10+var_s0]                            ; +0x14, 0x102e38\nADD             X29, SP, #0x10                                         ; +0x18, 0x102e3c\nLDR             W9, [X19,#0x14]                                        ; +0x1c, 0x102e40\nCMP             W8, W9                                                 ; +0x20, 0x102e44\nB.GE            loc_102F34                                             ; +0x24, 0x102e48\nLDR             W9, [X19,#0x54]                                        ; +0x28, 0x102e4c\nLDR             W10, [X19,#0x18]                                       ; +0x2c, 0x102e50\nLDR             W11, [X19,#0x20]                                       ; +0x30, 0x102e54\nLDR             W14, [X19,#0x10]                                       ; +0x34, 0x102e58\nADD             W9, W9, W8                                             ; +0x38, 0x102e5c\nADD             W9, W9, W10                                            ; +0x3c, 0x102e60\nSDIV            W10, W9, W11                                           ; +0x40, 0x102e64\nLDR             X13, [X19,#0x60]                                       ; +0x44, 0x102e68\nMSUB            W9, W10, W11, W9                                       ; +0x48, 0x102e6c\nLDP             X12, X11, [X19,#0x70]                                  ; +0x4c, 0x102e70\nADD             W10, W14, #1                                           ; +0x50, 0x102e74\nMUL             W9, W10, W9                                            ; +0x54, 0x102e78\nMUL             W10, W10, W8                                           ; +0x58, 0x102e7c\nADD             X12, X12, W10,SXTW#3                                   ; +0x5c, 0x102e80\nADD             X13, X13, W9,SXTW#3                                    ; +0x60, 0x102e84\nASR             W14, W14, #2                                           ; +0x64, 0x102e88\nCBZ             W14, loc_102EE0                                        ; +0x68, 0x102e8c\nLDP             Q1, Q2, [X13],#0x20                                    ; +0x6c, 0x102e90\nLDP             Q3, Q4, [X12],#0x20                                    ; +0x70, 0x102e94\nLDP             Q5, Q6, [X11]                                          ; +0x74, 0x102e98\nSUB             W14, W14, #1                                           ; +0x78, 0x102e9c\nTRN1            V7.4S, V1.4S, V1.4S                                    ; +0x7c, 0x102ea0\nTRN2            V1.4S, V1.4S, V1.4S                                    ; +0x80, 0x102ea4\nFMUL            V7.4S, V3.4S, V7.4S                                    ; +0x84, 0x102ea8\nREV64           V3.4S, V3.4S                                           ; +0x88, 0x102eac\nFMUL            V1.4S, V1.4S, V0.4S                                    ; +0x8c, 0x102eb0\nFMLA            V7.4S, V3.4S, V1.4S                                    ; +0x90, 0x102eb4\nTRN1            V1.4S, V2.4S, V2.4S                                    ; +0x94, 0x102eb8\nTRN2            V2.4S, V2.4S, V2.4S                                    ; +0x98, 0x102ebc\nREV64           V3.4S, V4.4S                                           ; +0x9c, 0x102ec0\nFMUL            V1.4S, V4.4S, V1.4S                                    ; +0xa0, 0x102ec4\nFMUL            V2.4S, V2.4S, V0.4S                                    ; +0xa4, 0x102ec8\nFMLA            V1.4S, V3.4S, V2.4S                                    ; +0xa8, 0x102ecc\nFADD            V2.4S, V7.4S, V5.4S                                    ; +0xac, 0x102ed0\nFADD            V1.4S, V1.4S, V6.4S                                    ; +0xb0, 0x102ed4\nSTP             Q2, Q1, [X11],#0x20                                    ; +0xb4, 0x102ed8\nCBNZ            W14, loc_102E90                                        ; +0xb8, 0x102edc\nLDRSW           X11, [X19,#0x10]                                       ; +0xbc, 0x102ee0\nLDR             X12, [X19,#0x70]                                       ; +0xc0, 0x102ee4\nLDR             X13, [X19,#0x60]                                       ; +0xc4, 0x102ee8\nADD             W8, W8, #1                                             ; +0xc8, 0x102eec\nADD             W10, W11, W10                                          ; +0xcc, 0x102ef0\nADD             X10, X12, W10,SXTW#3                                   ; +0xd0, 0x102ef4\nLD1R            {V1.2S}, [X10],#4                                      ; +0xd4, 0x102ef8\nADD             W9, W11, W9                                            ; +0xd8, 0x102efc\nLDR             D2, [X13,W9,SXTW#3]                                    ; +0xdc, 0x102f00\nLDR             X9, [X19,#0x78]                                        ; +0xe0, 0x102f04\nLDR             S3, [X10]                                              ; +0xe4, 0x102f08\nFMUL            V1.2S, V2.2S, V1.2S                                    ; +0xe8, 0x102f0c\nREV64           V2.2S, V2.2S                                           ; +0xec, 0x102f10\nLDR             D4, [X9,X11,LSL#3]                                     ; +0xf0, 0x102f14\nFMUL            V2.2S, V2.2S, V3.S[0]                                  ; +0xf4, 0x102f18\nFSUB            V3.2S, V1.2S, V2.2S                                    ; +0xf8, 0x102f1c\nFADD            V1.2S, V1.2S, V2.2S                                    ; +0xfc, 0x102f20\nINS             V3.S[1], V1.S[1]                                       ; +0x100, 0x102f24\nFADD            V1.2S, V3.2S, V4.2S                                    ; +0x104, 0x102f28\nSTR             D1, [X9,X11,LSL#3]                                     ; +0x108, 0x102f2c\nB               loc_102E40                                             ; +0x10c, 0x102f30\nLDR             X1, [X19,#0x78]                                        ; +0x110, 0x102f34\nLDRSW           X8, [X19,#0x24]                                        ; +0x114, 0x102f38\nLDR             W9, [X19,#0x10]                                        ; +0x118, 0x102f3c\nLDR             S0, [X1,#0x14]                                         ; +0x11c, 0x102f40\nADD             X10, X1, X8,LSL#3                                      ; +0x120, 0x102f44\nLSL             X8, X8, #3                                             ; +0x124, 0x102f48\nASR             W9, W9, #2                                             ; +0x128, 0x102f4c\nFNEG            S0, S0                                                 ; +0x12c, 0x102f50\nSTUR            S0, [X10,#-0xC]                                        ; +0x130, 0x102f54\nLDR             S0, [X1,#0x1C]                                         ; +0x134, 0x102f58\nSUB             X8, X8, #0x1C                                          ; +0x138, 0x102f5c\nSUB             W9, W9, #1                                             ; +0x13c, 0x102f60\nFNEG            S0, S0                                                 ; +0x140, 0x102f64\nSTUR            S0, [X10,#-0x14]                                       ; +0x144, 0x102f68\nMOV             W10, #0x24 ; '$'                                       ; +0x148, 0x102f6c\nADD             X12, X1, X10                                           ; +0x14c, 0x102f70\nLDR             S0, [X12]                                              ; +0x150, 0x102f74\nADD             X11, X1, X8                                            ; +0x154, 0x102f78\nFNEG            S0, S0                                                 ; +0x158, 0x102f7c\nSTR             S0, [X11]                                              ; +0x15c, 0x102f80\nCBZ             W9, loc_102FBC                                         ; +0x160, 0x102f84\nLDR             S0, [X12,#8]                                           ; +0x164, 0x102f88\nSUB             X8, X8, #0x20 ; ' '                                    ; +0x168, 0x102f8c\nADD             X10, X10, #0x20 ; ' '                                  ; +0x16c, 0x102f90\nSUB             W9, W9, #1                                             ; +0x170, 0x102f94\nFNEG            S0, S0                                                 ; +0x174, 0x102f98\nSTUR            S0, [X11,#-8]                                          ; +0x178, 0x102f9c\nLDR             S0, [X12,#0x10]                                        ; +0x17c, 0x102fa0\nFNEG            S0, S0                                                 ; +0x180, 0x102fa4\nSTUR            S0, [X11,#-0x10]                                       ; +0x184, 0x102fa8\nLDR             S0, [X12,#0x18]                                        ; +0x188, 0x102fac\nFNEG            S0, S0                                                 ; +0x18c, 0x102fb0\nSTUR            S0, [X11,#-0x18]                                       ; +0x190, 0x102fb4\nB               loc_102F70                                             ; +0x194, 0x102fb8\nLDR             X0, [X19,#0x48]                                        ; +0x198, 0x102fbc\nLDR             X2, [X19,#0x80]                                        ; +0x19c, 0x102fc0\nMOV             W4, #1                                                 ; +0x1a0, 0x102fc4\nMOV             X3, XZR                                                ; +0x1a4, 0x102fc8\nBL              sub_7259C                                              ; +0x1a8, 0x102fcc\nCBNZ            W0, loc_103044                                         ; +0x1ac, 0x102fd0\nLDR             S0, [X19,#0x24]                                        ; +0x1b0, 0x102fd4\nLDRSW           X10, [X19,#0x5C]                                       ; +0x1b4, 0x102fd8\nLDP             X11, X12, [X19,#0x38]                                  ; +0x1b8, 0x102fdc\nLDRSW           X13, [X19,#0x10]                                       ; +0x1bc, 0x102fe0\nLDR             X9, [X19,#0x80]                                        ; +0x1c0, 0x102fe4\nFMOV            S1, #1.0                                               ; +0x1c4, 0x102fe8\nSCVTF           S0, S0                                                 ; +0x1c8, 0x102fec\nFDIV            S0, S1, S0                                             ; +0x1cc, 0x102ff0\nMOV             W8, WZR                                                ; +0x1d0, 0x102ff4\nADD             X10, X11, X10,LSL#2                                    ; +0x1d4, 0x102ff8\nDUP             V0.4S, V0.S[0]                                         ; +0x1d8, 0x102ffc\nLSL             X11, X13, #2                                           ; +0x1dc, 0x103000\nCMP             W8, W13                                                ; +0x1e0, 0x103004\nB.GE            loc_103040                                             ; +0x1e4, 0x103008\nMOV             X14, X12                                               ; +0x1e8, 0x10300c\nLDR             Q1, [X9]                                               ; +0x1ec, 0x103010\nLDR             Q2, [X14],#0x10                                        ; +0x1f0, 0x103014\nLDR             Q3, [X9,X11]                                           ; +0x1f4, 0x103018\nADD             X9, X9, #0x10                                          ; +0x1f8, 0x10301c\nADD             W8, W8, #4                                             ; +0x1fc, 0x103020\nFADD            V1.4S, V2.4S, V1.4S                                    ; +0x200, 0x103024\nFMUL            V1.4S, V1.4S, V0.4S                                    ; +0x204, 0x103028\nSTR             Q3, [X12]                                              ; +0x208, 0x10302c\nSTR             Q1, [X10],#0x10                                        ; +0x20c, 0x103030\nLDR             W13, [X19,#0x10]                                       ; +0x210, 0x103034\nMOV             X12, X14                                               ; +0x214, 0x103038\nB               loc_103004                                             ; +0x218, 0x10303c\nMOV             W0, WZR                                                ; +0x21c, 0x103040\nLDP             X29, X30, [SP,#0x10+var_s0]                            ; +0x220, 0x103044\nLDR             X19, [SP+0x10+var_10],#0x20                            ; +0x224, 0x103048\nRET                                                                    ; +0x228, 0x10304c", "xrefs": ["sub_87AB0 @ 0x87ae8"], "is_objc": false, "is_arm32": false, "is_arm64": false, "bida_info": "8.0.0 @ https://github.com/Stazzical/BromaIDA", "bindings_info": "commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings"}