{"type": "func", "start": 1060944, "end": 1063444, "name": "sub_103050", "pseudocode": "// \n// sub_103050 from 0x103050 to 0x103a14 (2500 bytes)\n// \n// 3 xrefs:\n// > sub_103A14 @ 0x103a20\n// > sub_103A28 @ 0x103a34\n// > sub_103A3C @ 0x103a48\n// \n// This function is hookable on this platform!\n// \n// Using BromaIDA 8.0.0 @ https://github.com/Stazzical/BromaIDA\n// Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings\n// \n\n__int64 __fastcall sub_103050(__int64 a1, __int64 a2, __int64 a3, const float *a4, float *a5)\n{\n bool v5; // w8\n long double v6; // q0\n long double v7; // q1\n long double v8; // q2\n long double v9; // q3\n long double v10; // q4\n __int64 result; // x0\n __int64 v12; // x1\n int v13; // w2\n __int64 v14; // x3\n unsigned __int32 *v15; // x4\n int v16; // w6\n int v17; // w7\n __int64 v18; // x8\n int v19; // w9\n __int64 v20; // x10\n __int64 v21; // x11\n __int64 v22; // x12\n __int64 v23; // x13\n __int64 v24; // x14\n __int64 v25; // x15\n __int64 v26; // x16\n __int64 v27; // x17\n float32x4_t v28; // q0\n float32x4_t v29; // q1\n float32x4_t v30; // q2\n float32x4_t v31; // q3\n float32x4_t v32; // q4\n float32x4_t v33; // q5\n float32x4_t v34; // q6\n float32x4_t v35; // q7\n float32x4_t v36; // q16\n float32x4_t v37; // q17\n __int64 v38; // x5\n __int64 v39; // x5\n int v40; // w19\n __int64 i; // x20\n _DWORD *v42; // x21\n int v43; // w22\n float32x4_t v44; // q24\n float32x4_t v45; // q26\n float32x4_t v46; // q18\n float32x4_t v47; // q21\n float32x4_t v48; // q19\n float32x4_t v49; // q25\n float32x4_t v50; // q20\n float32x4_t v51; // q23\n __int64 v52; // x20\n float32x4_t v53; // q22\n float32x4_t v54; // q27\n float32x4_t v55; // q28\n float32x4_t v56; // q29\n float32x4_t v57; // q30\n int j; // w21\n float32x4_t v59; // q8\n float32x4_t v60; // q12\n float32x4_t v61; // q14\n float32x4_t v62; // q10\n float32x4_t v63; // q24\n float32x4_t v64; // q31\n float32x4_t v65; // q9\n float32x4_t v66; // q11\n float32x4_t v67; // q21\n float32x4_t v68; // q13\n float32x4_t v69; // q19\n float32x4_t v70; // q20\n float32x4_t v71; // q15\n float32x4_t v72; // q14\n __int64 v73; // x22\n float32x4_t v74; // q26\n float32x4_t v75; // q10\n __int64 k; // x20\n _DWORD *v77; // x22\n __int64 v78; // x1\n int v79; // w2\n __int64 v80; // x3\n int v81; // w6\n int v82; // w7\n __int64 v83; // x8\n int v84; // w9\n __int64 v85; // x10\n __int64 v86; // x11\n __int64 v87; // x12\n __int64 v88; // x13\n __int64 v89; // x14\n __int64 v90; // x15\n __int64 v91; // x16\n __int64 v92; // x17\n float32x4_t v93; // q0\n float32x4_t v94; // q1\n float32x4_t v95; // q2\n float32x4_t v96; // q3\n float32x4_t v97; // q4\n __int64 v98; // x4\n __int64 v99; // x4\n __int64 v100; // x5\n __int64 v101; // x5\n int v102; // w20\n __int64 m; // x21\n _DWORD *v104; // x22\n int v105; // w23\n float32x4_t v106; // q16\n float32x4_t v107; // q20\n float32x4_t v108; // q7\n float32x4_t v109; // q19\n float32x4_t v110; // q5\n float32x4_t v111; // q18\n float32x4_t v112; // q6\n float32x4_t v113; // q17\n __int64 v114; // x21\n __int64 v115; // x21\n int n; // w22\n float32x4_t v117; // q21\n float32x4_t v118; // q16\n float32x4_t v119; // q7\n float32x4_t v120; // q5\n float32x4_t v121; // q6\n float32x4_t v122; // q23\n float32x4_t v123; // q17\n float32x4_t v124; // q23\n float32x4_t v125; // q18\n float32x4_t v126; // q23\n float32x4_t v127; // q22\n __int64 v128; // x21\n int ii; // w22\n float32x4_t v130; // q21\n float32x4_t v131; // q16\n float32x4_t v132; // q7\n float32x4_t v133; // q5\n float32x4_t v134; // q6\n float32x4_t v135; // q23\n float32x4_t v136; // q17\n float32x4_t v137; // q23\n float32x4_t v138; // q18\n float32x4_t v139; // q23\n float32x4_t v140; // q22\n __int64 v141; // x21\n int jj; // w22\n float32x4_t v143; // q21\n __int64 v144; // x23\n float32x4_t v145; // q16\n float32x4_t v146; // q7\n float32x4_t v147; // q5\n float32x4_t v148; // q6\n float32x4_t v149; // q23\n float32x4_t v150; // q17\n float32x4_t v151; // q23\n float32x4_t v152; // q18\n float32x4_t v153; // q23\n float32x4_t v154; // q22\n __int64 v155; // x21\n int kk; // w22\n float32x4_t v157; // q21\n float32x4_t v158; // q16\n float32x4_t v159; // q7\n float32x4_t v160; // q5\n float32x4_t v161; // q6\n float32x4_t v162; // q23\n float32x4_t v163; // q17\n float32x4_t v164; // q23\n float32x4_t v165; // q18\n float32x4_t v166; // q23\n float32x4_t v167; // q22\n __int64 mm; // x21\n _DWORD *v169; // x23\n\n v5 = *a5 != 0.0 || a5[1] != 0.0 || a5[2] != 0.0 || a5[3] != 0.0 || a5[4] != 0.0;\n *(float32x4_t *)&v6 = vld1q_dup_f32(a4);\n *(float32x4_t *)&v7 = vld1q_dup_f32(a4 + 2);\n *(float32x4_t *)&v8 = vld1q_dup_f32(a4 + 3);\n *(float32x4_t *)&v9 = vld1q_dup_f32(a4 + 1);\n *(float32x4_t *)&v10 = vld1q_dup_f32(a4 + 4);\n if ( v5 )\n {\n result = sub_103A50(a1, a2, a3, a4, a5, 323584, v6, v7, v8, v9, v10);\n v39 = v38 + 2148;\n while ( v16 >= 1 )\n {\n v33.n128_u32[0] = *v15;\n v34.n128_u32[0] = v15[1];\n v35.n128_u32[0] = v15[2];\n v36.n128_u32[0] = v15[3];\n v37.n128_u32[0] = v15[4];\n v40 = v16 - 4;\n if ( v16 >= 4 )\n v16 = v19;\n for ( i = 0; i < v16; ++i )\n {\n v42 = *(_DWORD **)(v20 + 8 * i);\n *(_DWORD *)(v21 + 4 * i) = *v42;\n *(_DWORD *)(v22 + 4 * i) = v42[1];\n *(_DWORD *)(v23 + 4 * i) = v42[2];\n *(_DWORD *)(v24 + 4 * i) = v42[3];\n *(_DWORD *)(v25 + 4 * i) = v42[4];\n *(_DWORD *)(v26 + 4 * i) = v42[5];\n v43 = v42[6];\n LODWORD(v42) = v42[7];\n *(_DWORD *)(v27 + 4 * i) = v43;\n *(_DWORD *)(v14 + 4 * i) = (_DWORD)v42;\n }\n v45 = 0u;\n v44 = 0u;\n v46 = 0u;\n v47 = 0u;\n v49 = 0u;\n v48 = 0u;\n v51 = 0u;\n v50 = 0u;\n v52 = 0;\n v33 = vdupq_lane_s32((int32x2_t)v33.n128_u64[0], 0);\n v34 = vdupq_lane_s32((int32x2_t)v34.n128_u64[0], 0);\n v35 = vdupq_lane_s32((int32x2_t)v35.n128_u64[0], 0);\n v36 = vdupq_lane_s32((int32x2_t)v36.n128_u64[0], 0);\n v37 = vdupq_lane_s32((int32x2_t)v37.n128_u64[0], 0);\n v53 = 0u;\n v54 = 0u;\n v55 = 0u;\n v56 = 0u;\n v57 = 0u;\n for ( j = v13; j; v45 = vmlaq_f32(v75, v65, v59) )\n {\n v59 = *(float32x4_t *)(result + v52);\n v60 = vaddq_f32(v57, v28);\n v61 = vaddq_f32(v53, v32);\n v62 = vaddq_f32(v56, v31);\n v63 = vmlaq_f32(v44, v60, v59);\n v64 = vaddq_f32(v54, v30);\n v65 = vaddq_f32(v55, v29);\n v66 = vmulq_f32(v63, v61);\n if ( v17 >= 1 )\n {\n v67 = vmlaq_f32(v47, v60, v63);\n v68 = vaddq_f32(vmlaq_f32(vnegq_f32(vmulq_f32(v67, v64)), v62, v63), v46);\n v46 = vmlaq_f32(vnegq_f32(vmulq_f32(v67, v61)), v65, v63);\n if ( v17 != 1 )\n {\n v69 = vmlaq_f32(v48, v60, v67);\n v70 = vmlaq_f32(v50, v60, v69);\n v71 = vmulq_f32(v69, v61);\n v72 = vmulq_f32(v70, v61);\n v50 = vmlsq_f32(vmlaq_f32(v51, v62, v69), v64, v70);\n v51 = vmlaq_f32(vnegq_f32(v72), v65, v69);\n v48 = vmlsq_f32(vmlaq_f32(v49, v62, v67), v64, v69);\n v49 = vmlaq_f32(vnegq_f32(v71), v65, v67);\n }\n v47 = v68;\n }\n v73 = (unsigned int)(v16 - 1);\n v74 = vmlaq_f32(v45, v62, v59);\n v75 = vnegq_f32(v66);\n if ( (unsigned int)v73 <= 3 )\n __asm { BR X23 }\n v57 = vaddq_f32(v57, v33);\n v56 = vaddq_f32(v56, v34);\n v55 = vaddq_f32(v55, v35);\n v54 = vaddq_f32(v54, v36);\n v53 = vaddq_f32(v53, v37);\n --j;\n v52 += v18;\n v44 = vmlsq_f32(v74, v64, v63);\n }\n for ( k = 0; k < v16; ++k )\n {\n v77 = *(_DWORD **)(v20 + 8 * k);\n *v77 = *(_DWORD *)(v21 + 4 * k);\n v77[1] = *(_DWORD *)(v22 + 4 * k);\n v77[2] = *(_DWORD *)(v23 + 4 * k);\n v77[3] = *(_DWORD *)(v24 + 4 * k);\n v77[4] = *(_DWORD *)(v25 + 4 * k);\n v77[5] = *(_DWORD *)(v26 + 4 * k);\n v77[6] = *(_DWORD *)(v27 + 4 * k);\n v77[7] = *(_DWORD *)(v14 + 4 * k);\n *(_QWORD *)(v20 + 8 * k) = v77 + 32;\n }\n v12 += 16;\n result += 16;\n v16 = v40;\n }\n }\n else\n {\n result = sub_103A50(a1, a2, a3, a4, 323584, 323584, v6, v7, v8, v9, v10);\n v99 = v98 + 2136;\n v101 = v100 + 2140;\n while ( v81 >= 1 )\n {\n v102 = v81 - 4;\n if ( v81 >= 4 )\n v81 = v84;\n for ( m = 0; m < v81; ++m )\n {\n v104 = *(_DWORD **)(v85 + 8 * m);\n *(_DWORD *)(v86 + 4 * m) = *v104;\n *(_DWORD *)(v87 + 4 * m) = v104[1];\n *(_DWORD *)(v88 + 4 * m) = v104[2];\n *(_DWORD *)(v89 + 4 * m) = v104[3];\n *(_DWORD *)(v90 + 4 * m) = v104[4];\n *(_DWORD *)(v91 + 4 * m) = v104[5];\n v105 = v104[6];\n LODWORD(v104) = v104[7];\n *(_DWORD *)(v92 + 4 * m) = v105;\n *(_DWORD *)(v80 + 4 * m) = (_DWORD)v104;\n }\n v107 = 0u;\n v106 = 0u;\n v109 = 0u;\n v108 = 0u;\n v111 = 0u;\n v110 = 0u;\n v113 = 0u;\n v112 = 0u;\n v114 = (unsigned int)(v81 - 1);\n if ( v82 == 1 )\n {\n if ( (unsigned int)v114 <= 3 )\n __asm { BR X22 }\n }\n else\n {\n if ( !v82 )\n __asm { BR X22 }\n switch ( v81 )\n {\n case 1:\n v115 = 0;\n for ( n = v79; n; v115 += v83 )\n {\n v117 = *(float32x4_t *)(result + v115);\n --n;\n v118 = vmlaq_f32(v106, v93, v117);\n v119 = vmlaq_f32(v108, v93, v118);\n v120 = vmlaq_f32(v110, v93, v119);\n v121 = vmlaq_f32(v112, v93, v120);\n v122 = vmulq_f32(v121, v97);\n *(_DWORD *)(v78 + v115) = v121.n128_u32[0];\n v112 = vmlsq_f32(vmlaq_f32(v113, v96, v120), v95, v121);\n v123 = vnegq_f32(v122);\n v124 = vmulq_f32(v120, v97);\n v113 = vmlaq_f32(v123, v94, v120);\n v110 = vmlsq_f32(vmlaq_f32(v111, v96, v119), v95, v120);\n v125 = vnegq_f32(v124);\n v126 = vmulq_f32(v119, v97);\n v127 = vmulq_f32(v118, v97);\n v111 = vmlaq_f32(v125, v94, v119);\n v108 = vmlsq_f32(vmlaq_f32(v109, v96, v118), v95, v119);\n v109 = vmlaq_f32(vnegq_f32(v126), v94, v118);\n v106 = vmlsq_f32(vmlaq_f32(v107, v96, v117), v95, v118);\n v107 = vmlaq_f32(vnegq_f32(v127), v94, v117);\n }\n break;\n case 2:\n v128 = 0;\n for ( ii = v79; ii; v128 += v83 )\n {\n v130 = *(float32x4_t *)(result + v128);\n --ii;\n v131 = vmlaq_f32(v106, v93, v130);\n v132 = vmlaq_f32(v108, v93, v131);\n v133 = vmlaq_f32(v110, v93, v132);\n v134 = vmlaq_f32(v112, v93, v133);\n v135 = vmulq_f32(v134, v97);\n *(_QWORD *)(v78 + v128) = v134.n128_u64[0];\n v112 = vmlsq_f32(vmlaq_f32(v113, v96, v133), v95, v134);\n v136 = vnegq_f32(v135);\n v137 = vmulq_f32(v133, v97);\n v113 = vmlaq_f32(v136, v94, v133);\n v110 = vmlsq_f32(vmlaq_f32(v111, v96, v132), v95, v133);\n v138 = vnegq_f32(v137);\n v139 = vmulq_f32(v132, v97);\n v140 = vmulq_f32(v131, v97);\n v111 = vmlaq_f32(v138, v94, v132);\n v108 = vmlsq_f32(vmlaq_f32(v109, v96, v131), v95, v132);\n v109 = vmlaq_f32(vnegq_f32(v139), v94, v131);\n v106 = vmlsq_f32(vmlaq_f32(v107, v96, v130), v95, v131);\n v107 = vmlaq_f32(vnegq_f32(v140), v94, v130);\n }\n break;\n case 3:\n v141 = 0;\n for ( jj = v79; jj; v107 = vmlaq_f32(vnegq_f32(v154), v94, v143) )\n {\n v143 = *(float32x4_t *)(result + v141);\n v144 = v78 + v141;\n --jj;\n v141 += v83;\n v145 = vmlaq_f32(v106, v93, v143);\n v146 = vmlaq_f32(v108, v93, v145);\n v147 = vmlaq_f32(v110, v93, v146);\n v148 = vmlaq_f32(v112, v93, v147);\n *(_QWORD *)v144 = v148.n128_u64[0];\n v149 = vmulq_f32(v148, v97);\n *(_DWORD *)(v144 + 8) = v148.n128_u32[2];\n v112 = vmlsq_f32(vmlaq_f32(v113, v96, v147), v95, v148);\n v150 = vnegq_f32(v149);\n v151 = vmulq_f32(v147, v97);\n v113 = vmlaq_f32(v150, v94, v147);\n v110 = vmlsq_f32(vmlaq_f32(v111, v96, v146), v95, v147);\n v152 = vnegq_f32(v151);\n v153 = vmulq_f32(v146, v97);\n v154 = vmulq_f32(v145, v97);\n v111 = vmlaq_f32(v152, v94, v146);\n v108 = vmlsq_f32(vmlaq_f32(v109, v96, v145), v95, v146);\n v109 = vmlaq_f32(vnegq_f32(v153), v94, v145);\n v106 = vmlsq_f32(vmlaq_f32(v107, v96, v143), v95, v145);\n }\n break;\n case 4:\n v155 = 0;\n for ( kk = v79; kk; v155 += v83 )\n {\n v157 = *(float32x4_t *)(result + v155);\n --kk;\n v158 = vmlaq_f32(v106, v93, v157);\n v159 = vmlaq_f32(v108, v93, v158);\n v160 = vmlaq_f32(v110, v93, v159);\n v161 = vmlaq_f32(v112, v93, v160);\n v162 = vmulq_f32(v161, v97);\n *(float32x4_t *)(v78 + v155) = v161;\n v112 = vmlsq_f32(vmlaq_f32(v113, v96, v160), v95, v161);\n v163 = vnegq_f32(v162);\n v164 = vmulq_f32(v160, v97);\n v113 = vmlaq_f32(v163, v94, v160);\n v110 = vmlsq_f32(vmlaq_f32(v111, v96, v159), v95, v160);\n v165 = vnegq_f32(v164);\n v166 = vmulq_f32(v159, v97);\n v167 = vmulq_f32(v158, v97);\n v111 = vmlaq_f32(v165, v94, v159);\n v108 = vmlsq_f32(vmlaq_f32(v109, v96, v158), v95, v159);\n v109 = vmlaq_f32(vnegq_f32(v166), v94, v158);\n v106 = vmlsq_f32(vmlaq_f32(v107, v96, v157), v95, v158);\n v107 = vmlaq_f32(vnegq_f32(v167), v94, v157);\n }\n break;\n default:\n break;\n }\n }\n for ( mm = 0; mm < v81; ++mm )\n {\n v169 = *(_DWORD **)(v85 + 8 * mm);\n *v169 = *(_DWORD *)(v86 + 4 * mm);\n v169[1] = *(_DWORD *)(v87 + 4 * mm);\n v169[2] = *(_DWORD *)(v88 + 4 * mm);\n v169[3] = *(_DWORD *)(v89 + 4 * mm);\n v169[4] = *(_DWORD *)(v90 + 4 * mm);\n v169[5] = *(_DWORD *)(v91 + 4 * mm);\n v169[6] = *(_DWORD *)(v92 + 4 * mm);\n v169[7] = *(_DWORD *)(v80 + 4 * mm);\n *(_QWORD *)(v85 + 8 * mm) = v169 + 32;\n }\n v78 += 16;\n result += 16;\n v81 = v102;\n }\n }\n return result;\n}", "assembly": "; \n; sub_103050 from 0x103050 to 0x103a14 (2500 bytes)\n; \n; 3 xrefs:\n; > sub_103A14 @ 0x103a20\n; > sub_103A28 @ 0x103a34\n; > sub_103A3C @ 0x103a48\n; \n; This function is hookable on this platform!\n; \n; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA\n; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings\n; \n\nSUB SP, SP, #0x120 ; +0x0, 0x103050\nSTP D15, D14, [SP,#0x120+var_80] ; +0x4, 0x103054\nSTP D13, D12, [SP,#0x120+var_70] ; +0x8, 0x103058\nSTP D11, D10, [SP,#0x120+var_60] ; +0xc, 0x10305c\nSTP D9, D8, [SP,#0x120+var_50] ; +0x10, 0x103060\nSTP X24, X23, [SP,#0x120+var_30] ; +0x14, 0x103064\nSTP X22, X21, [SP,#0x120+var_20] ; +0x18, 0x103068\nSTP X20, X19, [SP,#0x120+var_10] ; +0x1c, 0x10306c\nLDR S0, [X4] ; +0x20, 0x103070\nSTR X28, [SP,#0x120+var_40] ; +0x24, 0x103074\nFCMP S0, #0.0 ; +0x28, 0x103078\nB.NE loc_1030A4 ; +0x2c, 0x10307c\nLDR S0, [X4,#4] ; +0x30, 0x103080\nFCMP S0, #0.0 ; +0x34, 0x103084\nB.NE loc_1030A4 ; +0x38, 0x103088\nLDR S0, [X4,#8] ; +0x3c, 0x10308c\nFCMP S0, #0.0 ; +0x40, 0x103090\nB.NE loc_1030A4 ; +0x44, 0x103094\nLDR S0, [X4,#0xC] ; +0x48, 0x103098\nFCMP S0, #0.0 ; +0x4c, 0x10309c\nB.EQ loc_103A04 ; +0x50, 0x1030a0\nMOV W8, #1 ; +0x54, 0x1030a4\nADRP X9, #xmmword_2F570@PAGE ; +0x58, 0x1030a8\nLDR Q1, [X9,#xmmword_2F570@PAGEOFF] ; +0x5c, 0x1030ac\nDUP V0.2D, X5 ; +0x60, 0x1030b0\nADD X9, X5, #0x60 ; '`' ; +0x64, 0x1030b4\nSTR X5, [SP,#0x120+var_A0] ; +0x68, 0x1030b8\nADD V0.2D, V0.2D, V1.2D ; +0x6c, 0x1030bc\nMOV X10, X3 ; +0x70, 0x1030c0\nSTR X9, [SP,#0x120+var_88] ; +0x74, 0x1030c4\nSTUR Q0, [SP,#0x120+var_98] ; +0x78, 0x1030c8\nLD1R {V0.4S}, [X10],#4 ; +0x7c, 0x1030cc\nADD X9, X3, #8 ; +0x80, 0x1030d0\nLD1R {V1.4S}, [X9] ; +0x84, 0x1030d4\nADD X9, X3, #0xC ; +0x88, 0x1030d8\nADD X11, X3, #0x10 ; +0x8c, 0x1030dc\nLD1R {V2.4S}, [X9] ; +0x90, 0x1030e0\nLD1R {V3.4S}, [X10] ; +0x94, 0x1030e4\nLD1R {V4.4S}, [X11] ; +0x98, 0x1030e8\nTBZ W8, #0, loc_103374 ; +0x9c, 0x1030ec\nADRP X5, #0x4F000 ; +0xa0, 0x1030f0\nMOV X19, X30 ; +0xa4, 0x1030f4\nBL sub_103A50 ; +0xa8, 0x1030f8\nMOV X30, X19 ; +0xac, 0x1030fc\nADD X5, X5, #0x864 ; +0xb0, 0x103100\nCMP W6, #1 ; +0xb4, 0x103104\nB.LT loc_1039DC ; +0xb8, 0x103108\nSTP XZR, XZR, [SP,#0x120+var_B0] ; +0xbc, 0x10310c\nSTP XZR, XZR, [SP,#0x120+var_C0] ; +0xc0, 0x103110\nSTP XZR, XZR, [SP,#0x120+var_D0] ; +0xc4, 0x103114\nSTP XZR, XZR, [SP,#0x120+var_E0] ; +0xc8, 0x103118\nSTP XZR, XZR, [SP,#0x120+var_F0] ; +0xcc, 0x10311c\nSTP XZR, XZR, [SP,#0x120+var_100] ; +0xd0, 0x103120\nSTP XZR, XZR, [SP,#0x120+var_110] ; +0xd4, 0x103124\nSTP XZR, XZR, [SP,#0x120+var_120] ; +0xd8, 0x103128\nLDP S5, S6, [X4] ; +0xdc, 0x10312c\nLDP S7, S16, [X4,#8] ; +0xe0, 0x103130\nLDR S17, [X4,#0x10] ; +0xe4, 0x103134\nSUBS W19, W6, #4 ; +0xe8, 0x103138\nCSEL W6, W6, W9, LT ; +0xec, 0x10313c\nMOV X20, XZR ; +0xf0, 0x103140\nSXTW X6, W6 ; +0xf4, 0x103144\nCMP X20, X6 ; +0xf8, 0x103148\nB.GE loc_103198 ; +0xfc, 0x10314c\nLDR X21, [X10,X20,LSL#3] ; +0x100, 0x103150\nLDR W22, [X21] ; +0x104, 0x103154\nSTR W22, [X11,X20,LSL#2] ; +0x108, 0x103158\nLDR W22, [X21,#4] ; +0x10c, 0x10315c\nSTR W22, [X12,X20,LSL#2] ; +0x110, 0x103160\nLDR W22, [X21,#8] ; +0x114, 0x103164\nSTR W22, [X13,X20,LSL#2] ; +0x118, 0x103168\nLDR W22, [X21,#0xC] ; +0x11c, 0x10316c\nSTR W22, [X14,X20,LSL#2] ; +0x120, 0x103170\nLDR W22, [X21,#0x10] ; +0x124, 0x103174\nSTR W22, [X15,X20,LSL#2] ; +0x128, 0x103178\nLDR W22, [X21,#0x14] ; +0x12c, 0x10317c\nSTR W22, [X16,X20,LSL#2] ; +0x130, 0x103180\nLDP W22, W21, [X21,#0x18] ; +0x134, 0x103184\nSTR W22, [X17,X20,LSL#2] ; +0x138, 0x103188\nSTR W21, [X3,X20,LSL#2] ; +0x13c, 0x10318c\nADD X20, X20, #1 ; +0x140, 0x103190\nB loc_103148 ; +0x144, 0x103194\nLDP Q26, Q24, [SP,#0x120+var_C0] ; +0x148, 0x103198\nLDP Q18, Q21, [SP,#0x120+var_E0] ; +0x14c, 0x10319c\nLDP Q25, Q19, [SP,#0x120+var_100] ; +0x150, 0x1031a0\nLDP Q23, Q20, [SP,#0x120+var_120] ; +0x154, 0x1031a4\nMOV X20, XZR ; +0x158, 0x1031a8\nDUP V5.4S, V5.S[0] ; +0x15c, 0x1031ac\nDUP V6.4S, V6.S[0] ; +0x160, 0x1031b0\nDUP V7.4S, V7.S[0] ; +0x164, 0x1031b4\nDUP V16.4S, V16.S[0] ; +0x168, 0x1031b8\nDUP V17.4S, V17.S[0] ; +0x16c, 0x1031bc\nMOVI V22.2D, #0 ; +0x170, 0x1031c0\nMOVI V27.2D, #0 ; +0x174, 0x1031c4\nMOVI V28.2D, #0 ; +0x178, 0x1031c8\nMOVI V29.2D, #0 ; +0x17c, 0x1031cc\nMOVI V30.2D, #0 ; +0x180, 0x1031d0\nMOV W21, W2 ; +0x184, 0x1031d4\nCBZ W21, loc_1032F4 ; +0x188, 0x1031d8\nLDR Q8, [X0,X20] ; +0x18c, 0x1031dc\nFADD V12.4S, V30.4S, V0.4S ; +0x190, 0x1031e0\nFADD V14.4S, V22.4S, V4.4S ; +0x194, 0x1031e4\nFADD V10.4S, V29.4S, V3.4S ; +0x198, 0x1031e8\nFMLA V24.4S, V12.4S, V8.4S ; +0x19c, 0x1031ec\nFADD V31.4S, V27.4S, V2.4S ; +0x1a0, 0x1031f0\nFADD V9.4S, V28.4S, V1.4S ; +0x1a4, 0x1031f4\nCMP W7, #1 ; +0x1a8, 0x1031f8\nFMUL V11.4S, V24.4S, V14.4S ; +0x1ac, 0x1031fc\nB.LT loc_103234 ; +0x1b0, 0x103200\nFMLA V21.4S, V12.4S, V24.4S ; +0x1b4, 0x103204\nFMUL V13.4S, V21.4S, V31.4S ; +0x1b8, 0x103208\nFNEG V13.4S, V13.4S ; +0x1bc, 0x10320c\nFMUL V15.4S, V21.4S, V14.4S ; +0x1c0, 0x103210\nFMLA V13.4S, V10.4S, V24.4S ; +0x1c4, 0x103214\nFADD V13.4S, V13.4S, V18.4S ; +0x1c8, 0x103218\nFNEG V18.4S, V15.4S ; +0x1cc, 0x10321c\nCMP W7, #1 ; +0x1d0, 0x103220\nFMLA V18.4S, V9.4S, V24.4S ; +0x1d4, 0x103224\nB.NE loc_10323C ; +0x1d8, 0x103228\nMOV V12.16B, V21.16B ; +0x1dc, 0x10322c\nB loc_103278 ; +0x1e0, 0x103230\nMOV V12.16B, V24.16B ; +0x1e4, 0x103234\nB loc_10327C ; +0x1e8, 0x103238\nFMLA V19.4S, V12.4S, V21.4S ; +0x1ec, 0x10323c\nFMLA V20.4S, V12.4S, V19.4S ; +0x1f0, 0x103240\nFMLA V23.4S, V10.4S, V19.4S ; +0x1f4, 0x103244\nFMLA V25.4S, V10.4S, V21.4S ; +0x1f8, 0x103248\nFMUL V15.4S, V19.4S, V14.4S ; +0x1fc, 0x10324c\nFMLS V23.4S, V31.4S, V20.4S ; +0x200, 0x103250\nFMUL V14.4S, V20.4S, V14.4S ; +0x204, 0x103254\nFMLS V25.4S, V31.4S, V19.4S ; +0x208, 0x103258\nMOV V12.16B, V20.16B ; +0x20c, 0x10325c\nMOV V20.16B, V23.16B ; +0x210, 0x103260\nFNEG V23.4S, V14.4S ; +0x214, 0x103264\nFMLA V23.4S, V9.4S, V19.4S ; +0x218, 0x103268\nMOV V19.16B, V25.16B ; +0x21c, 0x10326c\nFNEG V25.4S, V15.4S ; +0x220, 0x103270\nFMLA V25.4S, V9.4S, V21.4S ; +0x224, 0x103274\nMOV V21.16B, V13.16B ; +0x228, 0x103278\nSUB W22, W6, #1 ; +0x22c, 0x10327c\nFMLA V26.4S, V10.4S, V8.4S ; +0x230, 0x103280\nCMP W22, #3 ; +0x234, 0x103284\nFNEG V10.4S, V11.4S ; +0x238, 0x103288\nB.HI loc_1032C4 ; +0x23c, 0x10328c\nADR X23, loc_1032A0 ; +0x240, 0x103290\nLDRB W24, [X5,X22] ; +0x244, 0x103294\nADD X23, X23, X24,LSL#2 ; +0x248, 0x103298\nBR X23 ; +0x24c, 0x10329c\nSTR S12, [X1,X20] ; +0x250, 0x1032a0\nB loc_1032C4 ; +0x254, 0x1032a4\nSTR D12, [X1,X20] ; +0x258, 0x1032a8\nB loc_1032C4 ; +0x25c, 0x1032ac\nADD X22, X1, X20 ; +0x260, 0x1032b0\nSTR D12, [X22],#8 ; +0x264, 0x1032b4\nST1 {V12.S}[2], [X22] ; +0x268, 0x1032b8\nB loc_1032C4 ; +0x26c, 0x1032bc\nSTR Q12, [X1,X20] ; +0x270, 0x1032c0\nFMLA V10.4S, V9.4S, V8.4S ; +0x274, 0x1032c4\nFMLS V26.4S, V31.4S, V24.4S ; +0x278, 0x1032c8\nFADD V30.4S, V30.4S, V5.4S ; +0x27c, 0x1032cc\nFADD V29.4S, V29.4S, V6.4S ; +0x280, 0x1032d0\nFADD V28.4S, V28.4S, V7.4S ; +0x284, 0x1032d4\nFADD V27.4S, V27.4S, V16.4S ; +0x288, 0x1032d8\nFADD V22.4S, V22.4S, V17.4S ; +0x28c, 0x1032dc\nSUB W21, W21, #1 ; +0x290, 0x1032e0\nADD X20, X20, X8 ; +0x294, 0x1032e4\nMOV V24.16B, V26.16B ; +0x298, 0x1032e8\nMOV V26.16B, V10.16B ; +0x29c, 0x1032ec\nCBNZ W21, loc_1031DC ; +0x2a0, 0x1032f0\nMOV X20, XZR ; +0x2a4, 0x1032f4\nSTP Q26, Q24, [SP,#0x120+var_C0] ; +0x2a8, 0x1032f8\nSTP Q18, Q21, [SP,#0x120+var_E0] ; +0x2ac, 0x1032fc\nSTP Q25, Q19, [SP,#0x120+var_100] ; +0x2b0, 0x103300\nSTP Q23, Q20, [SP,#0x120+var_120] ; +0x2b4, 0x103304\nCMP X20, X6 ; +0x2b8, 0x103308\nB.GE loc_103364 ; +0x2bc, 0x10330c\nLDR W21, [X11,X20,LSL#2] ; +0x2c0, 0x103310\nLDR X22, [X10,X20,LSL#3] ; +0x2c4, 0x103314\nSTR W21, [X22] ; +0x2c8, 0x103318\nLDR W21, [X12,X20,LSL#2] ; +0x2cc, 0x10331c\nSTR W21, [X22,#4] ; +0x2d0, 0x103320\nLDR W21, [X13,X20,LSL#2] ; +0x2d4, 0x103324\nSTR W21, [X22,#8] ; +0x2d8, 0x103328\nLDR W21, [X14,X20,LSL#2] ; +0x2dc, 0x10332c\nSTR W21, [X22,#0xC] ; +0x2e0, 0x103330\nLDR W21, [X15,X20,LSL#2] ; +0x2e4, 0x103334\nSTR W21, [X22,#0x10] ; +0x2e8, 0x103338\nLDR W21, [X16,X20,LSL#2] ; +0x2ec, 0x10333c\nSTR W21, [X22,#0x14] ; +0x2f0, 0x103340\nLDR W21, [X17,X20,LSL#2] ; +0x2f4, 0x103344\nSTR W21, [X22,#0x18] ; +0x2f8, 0x103348\nLDR W21, [X3,X20,LSL#2] ; +0x2fc, 0x10334c\nSTR W21, [X22,#0x1C] ; +0x300, 0x103350\nADD X21, X22, #0x80 ; +0x304, 0x103354\nSTR X21, [X10,X20,LSL#3] ; +0x308, 0x103358\nADD X20, X20, #1 ; +0x30c, 0x10335c\nB loc_103308 ; +0x310, 0x103360\nADD X1, X1, #0x10 ; +0x314, 0x103364\nADD X0, X0, #0x10 ; +0x318, 0x103368\nMOV W6, W19 ; +0x31c, 0x10336c\nB loc_103104 ; +0x320, 0x103370\nADRP X4, #0x4F000 ; +0x324, 0x103374\nADRP X5, #0x4F000 ; +0x328, 0x103378\nADRP X19, #jpt_10351C@PAGE ; +0x32c, 0x10337c\nMOV X20, X30 ; +0x330, 0x103380\nBL sub_103A50 ; +0x334, 0x103384\nMOV X30, X20 ; +0x338, 0x103388\nADD X4, X4, #0x858 ; +0x33c, 0x10338c\nADD X5, X5, #0x85C ; +0x340, 0x103390\nADD X19, X19, #jpt_10351C@PAGEOFF ; +0x344, 0x103394\nCMP W6, #1 ; +0x348, 0x103398\nB.LT loc_1039DC ; +0x34c, 0x10339c\nSUBS W20, W6, #4 ; +0x350, 0x1033a0\nCSEL W6, W6, W9, LT ; +0x354, 0x1033a4\nMOV X21, XZR ; +0x358, 0x1033a8\nSXTW X6, W6 ; +0x35c, 0x1033ac\nSTP XZR, XZR, [SP,#0x120+var_B0] ; +0x360, 0x1033b0\nSTP XZR, XZR, [SP,#0x120+var_C0] ; +0x364, 0x1033b4\nSTP XZR, XZR, [SP,#0x120+var_D0] ; +0x368, 0x1033b8\nSTP XZR, XZR, [SP,#0x120+var_E0] ; +0x36c, 0x1033bc\nSTP XZR, XZR, [SP,#0x120+var_F0] ; +0x370, 0x1033c0\nSTP XZR, XZR, [SP,#0x120+var_100] ; +0x374, 0x1033c4\nSTP XZR, XZR, [SP,#0x120+var_110] ; +0x378, 0x1033c8\nSTP XZR, XZR, [SP,#0x120+var_120] ; +0x37c, 0x1033cc\nCMP X21, X6 ; +0x380, 0x1033d0\nB.GE loc_103420 ; +0x384, 0x1033d4\nLDR X22, [X10,X21,LSL#3] ; +0x388, 0x1033d8\nLDR W23, [X22] ; +0x38c, 0x1033dc\nSTR W23, [X11,X21,LSL#2] ; +0x390, 0x1033e0\nLDR W23, [X22,#4] ; +0x394, 0x1033e4\nSTR W23, [X12,X21,LSL#2] ; +0x398, 0x1033e8\nLDR W23, [X22,#8] ; +0x39c, 0x1033ec\nSTR W23, [X13,X21,LSL#2] ; +0x3a0, 0x1033f0\nLDR W23, [X22,#0xC] ; +0x3a4, 0x1033f4\nSTR W23, [X14,X21,LSL#2] ; +0x3a8, 0x1033f8\nLDR W23, [X22,#0x10] ; +0x3ac, 0x1033fc\nSTR W23, [X15,X21,LSL#2] ; +0x3b0, 0x103400\nLDR W23, [X22,#0x14] ; +0x3b4, 0x103404\nSTR W23, [X16,X21,LSL#2] ; +0x3b8, 0x103408\nLDP W23, W22, [X22,#0x18] ; +0x3bc, 0x10340c\nSTR W23, [X17,X21,LSL#2] ; +0x3c0, 0x103410\nSTR W22, [X3,X21,LSL#2] ; +0x3c4, 0x103414\nADD X21, X21, #1 ; +0x3c8, 0x103418\nB loc_1033D0 ; +0x3cc, 0x10341c\nLDP Q20, Q16, [SP,#0x120+var_C0] ; +0x3d0, 0x103420\nLDP Q19, Q7, [SP,#0x120+var_E0] ; +0x3d4, 0x103424\nLDP Q18, Q5, [SP,#0x120+var_100] ; +0x3d8, 0x103428\nLDP Q17, Q6, [SP,#0x120+var_120] ; +0x3dc, 0x10342c\nSUB W21, W6, #1; switch 4 cases ; +0x3e0, 0x103430\nCMP W7, #1 ; +0x3e4, 0x103434\nB.EQ loc_103498 ; +0x3e8, 0x103438\nCMP W21, #3 ; +0x3ec, 0x10343c\nCBNZ W7, loc_10350C ; +0x3f0, 0x103440\nB.HI def_10351C; jumptable 000000000010351C default case ; +0x3f4, 0x103444\nADR X22, loc_103458 ; +0x3f8, 0x103448\nLDRB W23, [X5,X21] ; +0x3fc, 0x10344c\nADD X22, X22, X23,LSL#2 ; +0x400, 0x103450\nBR X22 ; +0x404, 0x103454\nMOV X21, XZR ; +0x408, 0x103458\nMOV W22, W2 ; +0x40c, 0x10345c\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x410, 0x103460\nLDR Q21, [X0,X21] ; +0x414, 0x103464\nSUB W22, W22, #1 ; +0x418, 0x103468\nFMLA V20.4S, V3.4S, V21.4S ; +0x41c, 0x10346c\nFMLA V16.4S, V0.4S, V21.4S ; +0x420, 0x103470\nFMUL V22.4S, V16.4S, V4.4S ; +0x424, 0x103474\nFMLS V20.4S, V2.4S, V16.4S ; +0x428, 0x103478\nSTR S16, [X1,X21] ; +0x42c, 0x10347c\nMOV V16.16B, V20.16B ; +0x430, 0x103480\nFNEG V20.4S, V22.4S ; +0x434, 0x103484\nFMLA V20.4S, V1.4S, V21.4S ; +0x438, 0x103488\nADD X21, X21, X8 ; +0x43c, 0x10348c\nCBNZ W22, loc_103464 ; +0x440, 0x103490\nB def_10351C; jumptable 000000000010351C default case ; +0x444, 0x103494\nCMP W21, #3 ; +0x448, 0x103498\nB.HI def_10351C; jumptable 000000000010351C default case ; +0x44c, 0x10349c\nADR X22, loc_1034B0 ; +0x450, 0x1034a0\nLDRB W23, [X4,X21] ; +0x454, 0x1034a4\nADD X22, X22, X23,LSL#2 ; +0x458, 0x1034a8\nBR X22 ; +0x45c, 0x1034ac\nMOV X21, XZR ; +0x460, 0x1034b0\nMOV W22, W2 ; +0x464, 0x1034b4\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x468, 0x1034b8\nLDR Q21, [X0,X21] ; +0x46c, 0x1034bc\nSUB W22, W22, #1 ; +0x470, 0x1034c0\nFMLA V16.4S, V0.4S, V21.4S ; +0x474, 0x1034c4\nFMLA V7.4S, V0.4S, V16.4S ; +0x478, 0x1034c8\nFMLA V19.4S, V3.4S, V16.4S ; +0x47c, 0x1034cc\nFMLA V20.4S, V3.4S, V21.4S ; +0x480, 0x1034d0\nFMLS V19.4S, V2.4S, V7.4S ; +0x484, 0x1034d4\nFMUL V23.4S, V7.4S, V4.4S ; +0x488, 0x1034d8\nFMUL V22.4S, V16.4S, V4.4S ; +0x48c, 0x1034dc\nFMLS V20.4S, V2.4S, V16.4S ; +0x490, 0x1034e0\nSTR S7, [X1,X21] ; +0x494, 0x1034e4\nMOV V7.16B, V19.16B ; +0x498, 0x1034e8\nFNEG V19.4S, V23.4S ; +0x49c, 0x1034ec\nFMLA V19.4S, V1.4S, V16.4S ; +0x4a0, 0x1034f0\nMOV V16.16B, V20.16B ; +0x4a4, 0x1034f4\nFNEG V20.4S, V22.4S ; +0x4a8, 0x1034f8\nFMLA V20.4S, V1.4S, V21.4S ; +0x4ac, 0x1034fc\nADD X21, X21, X8 ; +0x4b0, 0x103500\nCBNZ W22, loc_1034BC ; +0x4b4, 0x103504\nB def_10351C; jumptable 000000000010351C default case ; +0x4b8, 0x103508\nB.HI def_10351C; jumptable 000000000010351C default case ; +0x4bc, 0x10350c\nADR X22, loc_103520; jumptable 000000000010351C case 1 ; +0x4c0, 0x103510\nLDRB W23, [X19,X21] ; +0x4c4, 0x103514\nADD X22, X22, X23,LSL#2 ; +0x4c8, 0x103518\nBR X22; switch jump ; +0x4cc, 0x10351c\nMOV X21, XZR; jumptable 000000000010351C case 1 ; +0x4d0, 0x103520\nMOV W22, W2 ; +0x4d4, 0x103524\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x4d8, 0x103528\nLDR Q21, [X0,X21] ; +0x4dc, 0x10352c\nSUB W22, W22, #1 ; +0x4e0, 0x103530\nFMLA V16.4S, V0.4S, V21.4S ; +0x4e4, 0x103534\nFMLA V7.4S, V0.4S, V16.4S ; +0x4e8, 0x103538\nFMLA V5.4S, V0.4S, V7.4S ; +0x4ec, 0x10353c\nFMLA V6.4S, V0.4S, V5.4S ; +0x4f0, 0x103540\nFMLA V17.4S, V3.4S, V5.4S ; +0x4f4, 0x103544\nFMLA V18.4S, V3.4S, V7.4S ; +0x4f8, 0x103548\nFMLS V17.4S, V2.4S, V6.4S ; +0x4fc, 0x10354c\nFMUL V23.4S, V6.4S, V4.4S ; +0x500, 0x103550\nFMLA V19.4S, V3.4S, V16.4S ; +0x504, 0x103554\nFMLS V18.4S, V2.4S, V5.4S ; +0x508, 0x103558\nSTR S6, [X1,X21] ; +0x50c, 0x10355c\nMOV V6.16B, V17.16B ; +0x510, 0x103560\nFNEG V17.4S, V23.4S ; +0x514, 0x103564\nFMUL V23.4S, V5.4S, V4.4S ; +0x518, 0x103568\nFMLA V20.4S, V3.4S, V21.4S ; +0x51c, 0x10356c\nFMLS V19.4S, V2.4S, V7.4S ; +0x520, 0x103570\nFMLA V17.4S, V1.4S, V5.4S ; +0x524, 0x103574\nMOV V5.16B, V18.16B ; +0x528, 0x103578\nFNEG V18.4S, V23.4S ; +0x52c, 0x10357c\nFMUL V23.4S, V7.4S, V4.4S ; +0x530, 0x103580\nFMUL V22.4S, V16.4S, V4.4S ; +0x534, 0x103584\nFMLS V20.4S, V2.4S, V16.4S ; +0x538, 0x103588\nFMLA V18.4S, V1.4S, V7.4S ; +0x53c, 0x10358c\nMOV V7.16B, V19.16B ; +0x540, 0x103590\nFNEG V19.4S, V23.4S ; +0x544, 0x103594\nFMLA V19.4S, V1.4S, V16.4S ; +0x548, 0x103598\nMOV V16.16B, V20.16B ; +0x54c, 0x10359c\nFNEG V20.4S, V22.4S ; +0x550, 0x1035a0\nFMLA V20.4S, V1.4S, V21.4S ; +0x554, 0x1035a4\nADD X21, X21, X8 ; +0x558, 0x1035a8\nCBNZ W22, loc_10352C ; +0x55c, 0x1035ac\nB def_10351C; jumptable 000000000010351C default case ; +0x560, 0x1035b0\nMOV X21, XZR ; +0x564, 0x1035b4\nMOV W22, W2 ; +0x568, 0x1035b8\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x56c, 0x1035bc\nLDR Q21, [X0,X21] ; +0x570, 0x1035c0\nSUB W22, W22, #1 ; +0x574, 0x1035c4\nFMLA V20.4S, V3.4S, V21.4S ; +0x578, 0x1035c8\nFMLA V16.4S, V0.4S, V21.4S ; +0x57c, 0x1035cc\nFMUL V22.4S, V16.4S, V4.4S ; +0x580, 0x1035d0\nFMLS V20.4S, V2.4S, V16.4S ; +0x584, 0x1035d4\nSTR D16, [X1,X21] ; +0x588, 0x1035d8\nMOV V16.16B, V20.16B ; +0x58c, 0x1035dc\nFNEG V20.4S, V22.4S ; +0x590, 0x1035e0\nFMLA V20.4S, V1.4S, V21.4S ; +0x594, 0x1035e4\nADD X21, X21, X8 ; +0x598, 0x1035e8\nCBNZ W22, loc_1035C0 ; +0x59c, 0x1035ec\nB def_10351C; jumptable 000000000010351C default case ; +0x5a0, 0x1035f0\nMOV X21, XZR ; +0x5a4, 0x1035f4\nMOV W22, W2 ; +0x5a8, 0x1035f8\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x5ac, 0x1035fc\nLDR Q21, [X0,X21] ; +0x5b0, 0x103600\nADD X23, X1, X21 ; +0x5b4, 0x103604\nADD X24, X23, #8 ; +0x5b8, 0x103608\nSUB W22, W22, #1 ; +0x5bc, 0x10360c\nFMLA V20.4S, V3.4S, V21.4S ; +0x5c0, 0x103610\nFMLA V16.4S, V0.4S, V21.4S ; +0x5c4, 0x103614\nFMUL V22.4S, V16.4S, V4.4S ; +0x5c8, 0x103618\nFMLS V20.4S, V2.4S, V16.4S ; +0x5cc, 0x10361c\nSTR D16, [X23] ; +0x5d0, 0x103620\nST1 {V16.S}[2], [X24] ; +0x5d4, 0x103624\nMOV V16.16B, V20.16B ; +0x5d8, 0x103628\nFNEG V20.4S, V22.4S ; +0x5dc, 0x10362c\nFMLA V20.4S, V1.4S, V21.4S ; +0x5e0, 0x103630\nADD X21, X21, X8 ; +0x5e4, 0x103634\nCBNZ W22, loc_103600 ; +0x5e8, 0x103638\nB def_10351C; jumptable 000000000010351C default case ; +0x5ec, 0x10363c\nMOV X21, XZR ; +0x5f0, 0x103640\nMOV W22, W2 ; +0x5f4, 0x103644\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x5f8, 0x103648\nLDR Q21, [X0,X21] ; +0x5fc, 0x10364c\nSUB W22, W22, #1 ; +0x600, 0x103650\nFMLA V20.4S, V3.4S, V21.4S ; +0x604, 0x103654\nFMLA V16.4S, V0.4S, V21.4S ; +0x608, 0x103658\nFMUL V22.4S, V16.4S, V4.4S ; +0x60c, 0x10365c\nFMLS V20.4S, V2.4S, V16.4S ; +0x610, 0x103660\nSTR Q16, [X1,X21] ; +0x614, 0x103664\nMOV V16.16B, V20.16B ; +0x618, 0x103668\nFNEG V20.4S, V22.4S ; +0x61c, 0x10366c\nFMLA V20.4S, V1.4S, V21.4S ; +0x620, 0x103670\nADD X21, X21, X8 ; +0x624, 0x103674\nCBNZ W22, loc_10364C ; +0x628, 0x103678\nB def_10351C; jumptable 000000000010351C default case ; +0x62c, 0x10367c\nMOV X21, XZR ; +0x630, 0x103680\nMOV W22, W2 ; +0x634, 0x103684\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x638, 0x103688\nLDR Q21, [X0,X21] ; +0x63c, 0x10368c\nSUB W22, W22, #1 ; +0x640, 0x103690\nFMLA V16.4S, V0.4S, V21.4S ; +0x644, 0x103694\nFMLA V7.4S, V0.4S, V16.4S ; +0x648, 0x103698\nFMLA V19.4S, V3.4S, V16.4S ; +0x64c, 0x10369c\nFMLA V20.4S, V3.4S, V21.4S ; +0x650, 0x1036a0\nFMLS V19.4S, V2.4S, V7.4S ; +0x654, 0x1036a4\nFMUL V23.4S, V7.4S, V4.4S ; +0x658, 0x1036a8\nFMUL V22.4S, V16.4S, V4.4S ; +0x65c, 0x1036ac\nFMLS V20.4S, V2.4S, V16.4S ; +0x660, 0x1036b0\nSTR D7, [X1,X21] ; +0x664, 0x1036b4\nMOV V7.16B, V19.16B ; +0x668, 0x1036b8\nFNEG V19.4S, V23.4S ; +0x66c, 0x1036bc\nFMLA V19.4S, V1.4S, V16.4S ; +0x670, 0x1036c0\nMOV V16.16B, V20.16B ; +0x674, 0x1036c4\nFNEG V20.4S, V22.4S ; +0x678, 0x1036c8\nFMLA V20.4S, V1.4S, V21.4S ; +0x67c, 0x1036cc\nADD X21, X21, X8 ; +0x680, 0x1036d0\nCBNZ W22, loc_10368C ; +0x684, 0x1036d4\nB def_10351C; jumptable 000000000010351C default case ; +0x688, 0x1036d8\nMOV X21, XZR ; +0x68c, 0x1036dc\nMOV W22, W2 ; +0x690, 0x1036e0\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x694, 0x1036e4\nLDR Q21, [X0,X21] ; +0x698, 0x1036e8\nADD X23, X1, X21 ; +0x69c, 0x1036ec\nSUB W22, W22, #1 ; +0x6a0, 0x1036f0\nADD X21, X21, X8 ; +0x6a4, 0x1036f4\nFMLA V16.4S, V0.4S, V21.4S ; +0x6a8, 0x1036f8\nFMLA V7.4S, V0.4S, V16.4S ; +0x6ac, 0x1036fc\nFMLA V19.4S, V3.4S, V16.4S ; +0x6b0, 0x103700\nFMLA V20.4S, V3.4S, V21.4S ; +0x6b4, 0x103704\nSTR D7, [X23],#8 ; +0x6b8, 0x103708\nFMLS V19.4S, V2.4S, V7.4S ; +0x6bc, 0x10370c\nFMUL V23.4S, V7.4S, V4.4S ; +0x6c0, 0x103710\nFMUL V22.4S, V16.4S, V4.4S ; +0x6c4, 0x103714\nFMLS V20.4S, V2.4S, V16.4S ; +0x6c8, 0x103718\nST1 {V7.S}[2], [X23] ; +0x6cc, 0x10371c\nMOV V7.16B, V19.16B ; +0x6d0, 0x103720\nFNEG V19.4S, V23.4S ; +0x6d4, 0x103724\nFMLA V19.4S, V1.4S, V16.4S ; +0x6d8, 0x103728\nMOV V16.16B, V20.16B ; +0x6dc, 0x10372c\nFNEG V20.4S, V22.4S ; +0x6e0, 0x103730\nFMLA V20.4S, V1.4S, V21.4S ; +0x6e4, 0x103734\nCBNZ W22, loc_1036E8 ; +0x6e8, 0x103738\nB def_10351C; jumptable 000000000010351C default case ; +0x6ec, 0x10373c\nMOV X21, XZR ; +0x6f0, 0x103740\nMOV W22, W2 ; +0x6f4, 0x103744\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x6f8, 0x103748\nLDR Q21, [X0,X21] ; +0x6fc, 0x10374c\nSUB W22, W22, #1 ; +0x700, 0x103750\nFMLA V16.4S, V0.4S, V21.4S ; +0x704, 0x103754\nFMLA V7.4S, V0.4S, V16.4S ; +0x708, 0x103758\nFMLA V19.4S, V3.4S, V16.4S ; +0x70c, 0x10375c\nFMLA V20.4S, V3.4S, V21.4S ; +0x710, 0x103760\nFMLS V19.4S, V2.4S, V7.4S ; +0x714, 0x103764\nFMUL V23.4S, V7.4S, V4.4S ; +0x718, 0x103768\nFMUL V22.4S, V16.4S, V4.4S ; +0x71c, 0x10376c\nFMLS V20.4S, V2.4S, V16.4S ; +0x720, 0x103770\nSTR Q7, [X1,X21] ; +0x724, 0x103774\nMOV V7.16B, V19.16B ; +0x728, 0x103778\nFNEG V19.4S, V23.4S ; +0x72c, 0x10377c\nFMLA V19.4S, V1.4S, V16.4S ; +0x730, 0x103780\nMOV V16.16B, V20.16B ; +0x734, 0x103784\nFNEG V20.4S, V22.4S ; +0x738, 0x103788\nFMLA V20.4S, V1.4S, V21.4S ; +0x73c, 0x10378c\nADD X21, X21, X8 ; +0x740, 0x103790\nCBNZ W22, loc_10374C ; +0x744, 0x103794\nB def_10351C; jumptable 000000000010351C default case ; +0x748, 0x103798\nMOV X21, XZR; jumptable 000000000010351C case 2 ; +0x74c, 0x10379c\nMOV W22, W2 ; +0x750, 0x1037a0\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x754, 0x1037a4\nLDR Q21, [X0,X21] ; +0x758, 0x1037a8\nSUB W22, W22, #1 ; +0x75c, 0x1037ac\nFMLA V16.4S, V0.4S, V21.4S ; +0x760, 0x1037b0\nFMLA V7.4S, V0.4S, V16.4S ; +0x764, 0x1037b4\nFMLA V5.4S, V0.4S, V7.4S ; +0x768, 0x1037b8\nFMLA V6.4S, V0.4S, V5.4S ; +0x76c, 0x1037bc\nFMLA V17.4S, V3.4S, V5.4S ; +0x770, 0x1037c0\nFMLA V18.4S, V3.4S, V7.4S ; +0x774, 0x1037c4\nFMLS V17.4S, V2.4S, V6.4S ; +0x778, 0x1037c8\nFMUL V23.4S, V6.4S, V4.4S ; +0x77c, 0x1037cc\nFMLA V19.4S, V3.4S, V16.4S ; +0x780, 0x1037d0\nFMLS V18.4S, V2.4S, V5.4S ; +0x784, 0x1037d4\nSTR D6, [X1,X21] ; +0x788, 0x1037d8\nMOV V6.16B, V17.16B ; +0x78c, 0x1037dc\nFNEG V17.4S, V23.4S ; +0x790, 0x1037e0\nFMUL V23.4S, V5.4S, V4.4S ; +0x794, 0x1037e4\nFMLA V20.4S, V3.4S, V21.4S ; +0x798, 0x1037e8\nFMLS V19.4S, V2.4S, V7.4S ; +0x79c, 0x1037ec\nFMLA V17.4S, V1.4S, V5.4S ; +0x7a0, 0x1037f0\nMOV V5.16B, V18.16B ; +0x7a4, 0x1037f4\nFNEG V18.4S, V23.4S ; +0x7a8, 0x1037f8\nFMUL V23.4S, V7.4S, V4.4S ; +0x7ac, 0x1037fc\nFMUL V22.4S, V16.4S, V4.4S ; +0x7b0, 0x103800\nFMLS V20.4S, V2.4S, V16.4S ; +0x7b4, 0x103804\nFMLA V18.4S, V1.4S, V7.4S ; +0x7b8, 0x103808\nMOV V7.16B, V19.16B ; +0x7bc, 0x10380c\nFNEG V19.4S, V23.4S ; +0x7c0, 0x103810\nFMLA V19.4S, V1.4S, V16.4S ; +0x7c4, 0x103814\nMOV V16.16B, V20.16B ; +0x7c8, 0x103818\nFNEG V20.4S, V22.4S ; +0x7cc, 0x10381c\nFMLA V20.4S, V1.4S, V21.4S ; +0x7d0, 0x103820\nADD X21, X21, X8 ; +0x7d4, 0x103824\nCBNZ W22, loc_1037A8 ; +0x7d8, 0x103828\nB def_10351C; jumptable 000000000010351C default case ; +0x7dc, 0x10382c\nMOV X21, XZR; jumptable 000000000010351C case 3 ; +0x7e0, 0x103830\nMOV W22, W2 ; +0x7e4, 0x103834\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x7e8, 0x103838\nLDR Q21, [X0,X21] ; +0x7ec, 0x10383c\nADD X23, X1, X21 ; +0x7f0, 0x103840\nSUB W22, W22, #1 ; +0x7f4, 0x103844\nADD X21, X21, X8 ; +0x7f8, 0x103848\nFMLA V16.4S, V0.4S, V21.4S ; +0x7fc, 0x10384c\nFMLA V7.4S, V0.4S, V16.4S ; +0x800, 0x103850\nFMLA V5.4S, V0.4S, V7.4S ; +0x804, 0x103854\nFMLA V6.4S, V0.4S, V5.4S ; +0x808, 0x103858\nFMLA V17.4S, V3.4S, V5.4S ; +0x80c, 0x10385c\nSTR D6, [X23],#8 ; +0x810, 0x103860\nFMLA V18.4S, V3.4S, V7.4S ; +0x814, 0x103864\nFMLS V17.4S, V2.4S, V6.4S ; +0x818, 0x103868\nFMUL V23.4S, V6.4S, V4.4S ; +0x81c, 0x10386c\nFMLA V19.4S, V3.4S, V16.4S ; +0x820, 0x103870\nFMLS V18.4S, V2.4S, V5.4S ; +0x824, 0x103874\nST1 {V6.S}[2], [X23] ; +0x828, 0x103878\nMOV V6.16B, V17.16B ; +0x82c, 0x10387c\nFNEG V17.4S, V23.4S ; +0x830, 0x103880\nFMUL V23.4S, V5.4S, V4.4S ; +0x834, 0x103884\nFMLA V20.4S, V3.4S, V21.4S ; +0x838, 0x103888\nFMLS V19.4S, V2.4S, V7.4S ; +0x83c, 0x10388c\nFMLA V17.4S, V1.4S, V5.4S ; +0x840, 0x103890\nMOV V5.16B, V18.16B ; +0x844, 0x103894\nFNEG V18.4S, V23.4S ; +0x848, 0x103898\nFMUL V23.4S, V7.4S, V4.4S ; +0x84c, 0x10389c\nFMUL V22.4S, V16.4S, V4.4S ; +0x850, 0x1038a0\nFMLS V20.4S, V2.4S, V16.4S ; +0x854, 0x1038a4\nFMLA V18.4S, V1.4S, V7.4S ; +0x858, 0x1038a8\nMOV V7.16B, V19.16B ; +0x85c, 0x1038ac\nFNEG V19.4S, V23.4S ; +0x860, 0x1038b0\nFMLA V19.4S, V1.4S, V16.4S ; +0x864, 0x1038b4\nMOV V16.16B, V20.16B ; +0x868, 0x1038b8\nFNEG V20.4S, V22.4S ; +0x86c, 0x1038bc\nFMLA V20.4S, V1.4S, V21.4S ; +0x870, 0x1038c0\nCBNZ W22, loc_10383C ; +0x874, 0x1038c4\nB def_10351C; jumptable 000000000010351C default case ; +0x878, 0x1038c8\nMOV X21, XZR; jumptable 000000000010351C case 4 ; +0x87c, 0x1038cc\nMOV W22, W2 ; +0x880, 0x1038d0\nCBZ W22, def_10351C; jumptable 000000000010351C default case ; +0x884, 0x1038d4\nLDR Q21, [X0,X21] ; +0x888, 0x1038d8\nSUB W22, W22, #1 ; +0x88c, 0x1038dc\nFMLA V16.4S, V0.4S, V21.4S ; +0x890, 0x1038e0\nFMLA V7.4S, V0.4S, V16.4S ; +0x894, 0x1038e4\nFMLA V5.4S, V0.4S, V7.4S ; +0x898, 0x1038e8\nFMLA V6.4S, V0.4S, V5.4S ; +0x89c, 0x1038ec\nFMLA V17.4S, V3.4S, V5.4S ; +0x8a0, 0x1038f0\nFMLA V18.4S, V3.4S, V7.4S ; +0x8a4, 0x1038f4\nFMLS V17.4S, V2.4S, V6.4S ; +0x8a8, 0x1038f8\nFMUL V23.4S, V6.4S, V4.4S ; +0x8ac, 0x1038fc\nFMLA V19.4S, V3.4S, V16.4S ; +0x8b0, 0x103900\nFMLS V18.4S, V2.4S, V5.4S ; +0x8b4, 0x103904\nSTR Q6, [X1,X21] ; +0x8b8, 0x103908\nMOV V6.16B, V17.16B ; +0x8bc, 0x10390c\nFNEG V17.4S, V23.4S ; +0x8c0, 0x103910\nFMUL V23.4S, V5.4S, V4.4S ; +0x8c4, 0x103914\nFMLA V20.4S, V3.4S, V21.4S ; +0x8c8, 0x103918\nFMLS V19.4S, V2.4S, V7.4S ; +0x8cc, 0x10391c\nFMLA V17.4S, V1.4S, V5.4S ; +0x8d0, 0x103920\nMOV V5.16B, V18.16B ; +0x8d4, 0x103924\nFNEG V18.4S, V23.4S ; +0x8d8, 0x103928\nFMUL V23.4S, V7.4S, V4.4S ; +0x8dc, 0x10392c\nFMUL V22.4S, V16.4S, V4.4S ; +0x8e0, 0x103930\nFMLS V20.4S, V2.4S, V16.4S ; +0x8e4, 0x103934\nFMLA V18.4S, V1.4S, V7.4S ; +0x8e8, 0x103938\nMOV V7.16B, V19.16B ; +0x8ec, 0x10393c\nFNEG V19.4S, V23.4S ; +0x8f0, 0x103940\nFMLA V19.4S, V1.4S, V16.4S ; +0x8f4, 0x103944\nMOV V16.16B, V20.16B ; +0x8f8, 0x103948\nFNEG V20.4S, V22.4S ; +0x8fc, 0x10394c\nFMLA V20.4S, V1.4S, V21.4S ; +0x900, 0x103950\nADD X21, X21, X8 ; +0x904, 0x103954\nCBNZ W22, loc_1038D8 ; +0x908, 0x103958\nMOV X21, XZR; jumptable 000000000010351C default case ; +0x90c, 0x10395c\nSTP Q20, Q16, [SP,#0x120+var_C0] ; +0x910, 0x103960\nSTP Q19, Q7, [SP,#0x120+var_E0] ; +0x914, 0x103964\nSTP Q18, Q5, [SP,#0x120+var_100] ; +0x918, 0x103968\nSTP Q17, Q6, [SP,#0x120+var_120] ; +0x91c, 0x10396c\nCMP X21, X6 ; +0x920, 0x103970\nB.GE loc_1039CC ; +0x924, 0x103974\nLDR W22, [X11,X21,LSL#2] ; +0x928, 0x103978\nLDR X23, [X10,X21,LSL#3] ; +0x92c, 0x10397c\nSTR W22, [X23] ; +0x930, 0x103980\nLDR W22, [X12,X21,LSL#2] ; +0x934, 0x103984\nSTR W22, [X23,#4] ; +0x938, 0x103988\nLDR W22, [X13,X21,LSL#2] ; +0x93c, 0x10398c\nSTR W22, [X23,#8] ; +0x940, 0x103990\nLDR W22, [X14,X21,LSL#2] ; +0x944, 0x103994\nSTR W22, [X23,#0xC] ; +0x948, 0x103998\nLDR W22, [X15,X21,LSL#2] ; +0x94c, 0x10399c\nSTR W22, [X23,#0x10] ; +0x950, 0x1039a0\nLDR W22, [X16,X21,LSL#2] ; +0x954, 0x1039a4\nSTR W22, [X23,#0x14] ; +0x958, 0x1039a8\nLDR W22, [X17,X21,LSL#2] ; +0x95c, 0x1039ac\nSTR W22, [X23,#0x18] ; +0x960, 0x1039b0\nLDR W22, [X3,X21,LSL#2] ; +0x964, 0x1039b4\nSTR W22, [X23,#0x1C] ; +0x968, 0x1039b8\nADD X22, X23, #0x80 ; +0x96c, 0x1039bc\nSTR X22, [X10,X21,LSL#3] ; +0x970, 0x1039c0\nADD X21, X21, #1 ; +0x974, 0x1039c4\nB loc_103970 ; +0x978, 0x1039c8\nADD X1, X1, #0x10 ; +0x97c, 0x1039cc\nADD X0, X0, #0x10 ; +0x980, 0x1039d0\nMOV W6, W20 ; +0x984, 0x1039d4\nB loc_103398 ; +0x988, 0x1039d8\nLDP X20, X19, [SP,#0x120+var_10] ; +0x98c, 0x1039dc\nLDP X22, X21, [SP,#0x120+var_20] ; +0x990, 0x1039e0\nLDP X24, X23, [SP,#0x120+var_30] ; +0x994, 0x1039e4\nLDR X28, [SP,#0x120+var_40] ; +0x998, 0x1039e8\nLDP D9, D8, [SP,#0x120+var_50] ; +0x99c, 0x1039ec\nLDP D11, D10, [SP,#0x120+var_60] ; +0x9a0, 0x1039f0\nLDP D13, D12, [SP,#0x120+var_70] ; +0x9a4, 0x1039f4\nLDP D15, D14, [SP,#0x120+var_80] ; +0x9a8, 0x1039f8\nADD SP, SP, #0x120 ; +0x9ac, 0x1039fc\nRET ; +0x9b0, 0x103a00\nLDR S0, [X4,#0x10] ; +0x9b4, 0x103a04\nFCMP S0, #0.0 ; +0x9b8, 0x103a08\nCSET W8, NE ; +0x9bc, 0x103a0c\nB loc_1030A8 ; +0x9c0, 0x103a10", "xrefs": ["sub_103A14 @ 0x103a20", "sub_103A28 @ 0x103a34", "sub_103A3C @ 0x103a48"], "is_objc": false, "is_arm32": false, "is_arm64": false, "bida_info": "8.0.0 @ https://github.com/Stazzical/BromaIDA", "bindings_info": "commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings"}