{"type": "func", "start": 1064580, "end": 1065740, "name": "sub_103E84", "pseudocode": "// \n// sub_103E84 from 0x103e84 to 0x10430c (1160 bytes)\n// \n// 1 xrefs:\n// > @ 0x11f738\n// \n// This function is hookable on this platform!\n// \n// Using BromaIDA 8.0.0 @ https://github.com/Stazzical/BromaIDA\n// Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings\n// \n\n__int64 __fastcall sub_103E84(__int64 a1, __int64 a2, __int64 a3, int a4)\n{\n int v4; // w8\n unsigned __int64 v5; // x22\n __int64 v7; // x20\n unsigned int v9; // w23\n int v10; // w23\n long double v11; // q0\n float32x4_t v12; // q0\n __int64 v13; // x0\n __int64 v14; // x1\n int32x4_t v15; // q0\n int32x4_t v16; // q1\n int32x4_t v17; // q16\n uint32x4_t v18; // q3\n uint32x4_t v19; // q1\n int32x4_t v20; // q2\n uint32x4_t v21; // q16\n float32x4_t v22; // q4\n float32x4_t v23; // q5\n float32x4_t v24; // q7\n __int64 v25; // x23\n __int64 v26; // x22\n __int64 v27; // x0\n __int64 v28; // x1\n long double v29; // q0\n __int128 v30; // q1\n long double v31; // q0\n __int128 v32; // q1\n __int64 v33; // x8\n int v34; // w23\n int8x16_t v35; // q0\n int32x4_t v36; // q2\n int32x4_t v37; // q0\n __int64 v38; // x23\n __int64 v39; // x22\n int8x16_t v40; // q0\n float32x4_t v41; // q2\n int v42; // w22\n __int64 j; // x0\n int32x4_t v44; // q0\n int32x4_t v45; // q1\n int32x4_t v46; // q19\n uint32x4_t v47; // q3\n uint32x4_t v48; // q1\n int8x16_t v49; // q5\n int8x16_t v50; // q4\n int32x4_t v51; // q19\n int8x16_t v52; // q7\n int8x16_t v53; // q6\n int32x4_t v54; // q5\n uint32x4_t v55; // q7\n uint32x4_t v56; // q5\n int32x4_t v57; // q2\n uint32x4_t v58; // q19\n uint32x4_t v59; // q0\n uint32x4_t v60; // q2\n uint32x4_t v61; // q4\n float32x4_t v62; // q20\n float32x4_t v63; // q18\n float32x4_t v64; // q6\n float32x4_t v65; // q3\n float32x4_t v66; // q7\n float32x4_t v67; // q16\n float32x4_t v68; // q17\n float32x4_t v69; // q1\n float32x4_t v70; // q5\n float32x4_t v71; // q2\n float32x4_t v72; // q19\n float32x4_t v73; // q4\n float32x4_t v74; // q0\n float32x4_t v75; // q2\n float32x4_t v76; // q3\n float32x4_t v77; // q6\n float32x4_t v78; // q7\n int k; // w22\n float32x4_t v80; // q0\n int16x8_t i; // [xsp+40h] [xbp-B0h]\n float32x4_t v83; // [xsp+50h] [xbp-A0h]\n long double v84; // [xsp+50h] [xbp-A0h]\n int8x16_t v85; // [xsp+50h] [xbp-A0h]\n float32x4_t v86; // [xsp+60h] [xbp-90h]\n float32x4_t v87; // [xsp+60h] [xbp-90h]\n float32x4_t v88; // [xsp+60h] [xbp-90h]\n float32x4_t v89; // [xsp+70h] [xbp-80h]\n float32x4_t v90; // [xsp+80h] [xbp-70h]\n long double v91; // [xsp+90h] [xbp-60h]\n int8x16_t v92; // [xsp+A0h] [xbp-50h]\n int8x16_t v93; // [xsp+B0h] [xbp-40h]\n\n v4 = *(unsigned __int8 *)(a1 + 102);\n v91 = *(long double *)a1;\n v5 = (unsigned int)a4;\n v7 = a1;\n v90 = *(float32x4_t *)(a1 + 16);\n v9 = a4 >> 2;\n v89 = *(float32x4_t *)(a1 + 32);\n switch ( *(_BYTE *)(a1 + 100) )\n {\n case 0:\n case 1:\n while ( v9 )\n {\n v31 = sub_104768(a1);\n --v9;\n a1 = sub_10479C(v31, *(long double *)a2, v91);\n *(_OWORD *)a2 = v32;\n a2 = v33;\n }\n break;\n case 2:\n case 3:\n v34 = a4 >> 3;\n for ( i = vdupq_n_s16(-v4); v34; a2 += 32 )\n {\n v84 = *(long double *)a2;\n v87 = *(float32x4_t *)(a2 + 16);\n v35.n128_u64[0] = sub_103C94(v7, a3);\n --v34;\n v36 = vmlaq_f32(v90, vcvtq_f32_u32(vandq_s8(v35, *(int8x16_t *)&v91)), v89);\n v37 = vmlaq_f32(v90, vcvtq_f32_u32(vandq_s8(*(int8x16_t *)&v91, vshlq_s16(v35, i))), v89);\n *(float32x4_t *)a2 = vaddq_f32(vzip1q_s32(v36, v37), *(float32x4_t *)&v84);\n *(float32x4_t *)(a2 + 16) = vaddq_f32(vzip2q_s32(v36, v37), v87);\n }\n v38 = 0;\n v39 = (v5 >> 2) & 1;\n while ( (_DWORD)v39 != (_DWORD)v38 )\n {\n v88 = COERCE_FLOAT32X4_T(sub_104774(*(long double *)(a2 + 16 * v38)));\n v85 = COERCE_INT8X16_T(((long double (*)(void))sub_10430C)());\n *(long double *)&v40 = sub_10430C(v7, a3);\n v41.n128_u64[0] = vmlaq_f32(v90, vcvtq_f32_u32(vandq_s8(v85, *(int8x16_t *)&v91)), v89).n128_u64[0];\n v41.n128_u64[1] = vmlaq_f32(v90, vcvtq_f32_u32(vandq_s8(v40, *(int8x16_t *)&v91)), v89).n128_u64[0];\n *(float32x4_t *)(a2 + 16 * v38++) = vaddq_f32(v41, v88);\n }\n break;\n case 4:\n case 5:\n case 6:\n case 7:\n sub_104780();\n v10 = (int)v5 >> 4;\n sub_1047CC(v11);\n if ( (int)v5 >> 4 )\n {\n do\n {\n sub_104774(*(long double *)a2);\n v83 = *(float32x4_t *)(a2 + 32);\n v86 = *(float32x4_t *)(a2 + 48);\n sub_103C94(v13, v14);\n *(long double *)&v15 = sub_1047F0();\n v18 = vuzp1q_s32(v17, v16);\n v19 = vuzp2q_s32(v17, v16);\n v21 = vuzp1q_s32(v15, v20);\n v12 = vcvtq_f32_u32(vuzp2q_s32(v15, v20));\n *(float32x4_t *)(a2 + 32) = vmlaq_f32(vaddq_f32(v83, v24), vcvtq_f32_u32(v18), v89);\n *(float32x4_t *)(a2 + 48) = vmlaq_f32(vaddq_f32(v86, v24), vcvtq_f32_u32(v19), v89);\n *(float32x4_t *)a2 = vmlaq_f32(vaddq_f32(v22, v24), vcvtq_f32_u32(v21), v89);\n *(float32x4_t *)(a2 + 16) = vmlaq_f32(vaddq_f32(v23, v24), v12, v89);\n a2 += 64;\n --v10;\n }\n while ( v10 );\n }\n v25 = 0;\n v26 = (v5 >> 2) & 3;\n while ( (_DWORD)v26 != (_DWORD)v25 )\n {\n sub_104774(*(long double *)&v12);\n v29 = sub_10430C(v27, v28);\n sub_10479C(v29, *(long double *)(a2 + 16 * v25), v91);\n *(_OWORD *)(a2 + 16 * v25++) = v30;\n }\n break;\n case 8:\n v42 = a4 >> 5;\n for ( j = sub_1047CC(COERCE_LONG_DOUBLE(vdupq_n_s16(-6 * v4))); v42; a2 += 128 )\n {\n sub_104768(j);\n *(long double *)&v44 = sub_1047F0();\n v47 = vuzp1q_s32(v46, v45);\n v48 = vuzp2q_s32(v46, v45);\n v51 = vextq_s8(v50, vextq_s8(v49, v50, 8u), 8u);\n v50.n128_u64[1] = v49.n128_u64[0];\n v54 = vextq_s8(v53, vextq_s8(v52, v53, 8u), 8u);\n v53.n128_u64[1] = v52.n128_u64[0];\n v55 = vuzp1q_s32(v51, v54);\n v56 = vuzp2q_s32(v51, v54);\n v58 = vuzp1q_s32(v44, v57);\n v59 = vuzp2q_s32(v44, v57);\n v60 = vuzp1q_s32(v50, v53);\n v61 = vuzp2q_s32(v50, v53);\n v63 = vmlaq_f32(v62, vcvtq_f32_u32(v47), v89);\n v64 = vmlaq_f32(v62, vcvtq_f32_u32(v55), v89);\n v65 = vmlaq_f32(v62, vcvtq_f32_u32(v48), v89);\n v66 = vmlaq_f32(v62, vcvtq_f32_u32(v56), v89);\n v67 = vmlaq_f32(v62, vcvtq_f32_u32(v59), v89);\n v68 = vmlaq_f32(v62, vcvtq_f32_u32(v61), v89);\n v69 = vmlaq_f32(vaddq_f32(*(float32x4_t *)a2, v62), vcvtq_f32_u32(v58), v89);\n v70 = vmlaq_f32(vaddq_f32(*(float32x4_t *)(a2 + 16), v62), vcvtq_f32_u32(v60), v89);\n v71 = *(float32x4_t *)(a2 + 96);\n v72 = *(float32x4_t *)(a2 + 112);\n v73 = vaddq_f32(v64, *(float32x4_t *)(a2 + 80));\n v74 = vaddq_f32(v63, *(float32x4_t *)(a2 + 64));\n *(float32x4_t *)a2 = v69;\n *(float32x4_t *)(a2 + 16) = v70;\n v75 = vaddq_f32(v65, v71);\n v76 = vaddq_f32(v66, v72);\n v77 = *(float32x4_t *)(a2 + 32);\n v78 = *(float32x4_t *)(a2 + 48);\n *(float32x4_t *)(a2 + 64) = v74;\n *(float32x4_t *)(a2 + 80) = v73;\n *(float32x4_t *)(a2 + 96) = v75;\n *(float32x4_t *)(a2 + 112) = v76;\n --v42;\n *(float32x4_t *)(a2 + 32) = vaddq_f32(v67, v77);\n *(float32x4_t *)(a2 + 48) = vaddq_f32(v68, v78);\n }\n for ( k = (v9 >> 1) & 3; k; a2 += 32 )\n {\n j = sub_1047B8(j);\n --k;\n v92 = vandq_s8(v92, *(int8x16_t *)&v91);\n v93 = vandq_s8(v93, *(int8x16_t *)&v91);\n v80 = vaddq_f32(vmlaq_f32(v90, vcvtq_f32_u32(v92), v89), *(float32x4_t *)(a2 + 16));\n *(float32x4_t *)a2 = vaddq_f32(vmlaq_f32(v90, vcvtq_f32_u32(v93), v89), *(float32x4_t *)a2);\n *(float32x4_t *)(a2 + 16) = v80;\n }\n break;\n default:\n return 0;\n }\n return 0;\n}", "assembly": "; \n; sub_103E84 from 0x103e84 to 0x10430c (1160 bytes)\n; \n; 1 xrefs:\n; > @ 0x11f738\n; \n; This function is hookable on this platform!\n; \n; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA\n; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings\n; \n\nSUB SP, SP, #0x100 ; +0x0, 0x103e84\nSTP X22, X21, [SP,#0xF0+var_20] ; +0x4, 0x103e88\nSTP X20, X19, [SP,#0xF0+var_10] ; +0x8, 0x103e8c\nSTP X29, X30, [SP,#0xF0+var_s0] ; +0xc, 0x103e90\nLDRB W9, [X0,#0x64] ; +0x10, 0x103e94\nSTR X23, [SP,#0xF0+var_30] ; +0x14, 0x103e98\nADD X29, SP, #0xF0 ; +0x18, 0x103e9c\nCMP W9, #8; switch 9 cases ; +0x1c, 0x103ea0\nB.HI def_103EEC; jumptable 0000000000103EEC default case ; +0x20, 0x103ea4\nLDR Q0, [X0] ; +0x24, 0x103ea8\nLDRB W8, [X0,#0x66] ; +0x28, 0x103eac\nADRL X10, jpt_103EEC ; +0x2c, 0x103eb0\nSTUR Q0, [X29,#var_60] ; +0x34, 0x103eb8\nLDR Q0, [X0,#0x10] ; +0x38, 0x103ebc\nMOV W22, W3 ; +0x3c, 0x103ec0\nMOV X19, X2 ; +0x40, 0x103ec4\nMOV X20, X0 ; +0x44, 0x103ec8\nSTUR Q0, [X29,#var_70] ; +0x48, 0x103ecc\nLDR Q0, [X0,#0x20] ; +0x4c, 0x103ed0\nMOV X21, X1 ; +0x50, 0x103ed4\nASR W23, W3, #2 ; +0x54, 0x103ed8\nSTR Q0, [SP,#0xF0+var_80] ; +0x58, 0x103edc\nADR X11, loc_103EF0; jumptable 0000000000103EEC cases 4-7 ; +0x5c, 0x103ee0\nLDRB W12, [X10,X9] ; +0x60, 0x103ee4\nADD X11, X11, X12,LSL#2 ; +0x64, 0x103ee8\nBR X11; switch jump ; +0x68, 0x103eec\nBL sub_104780; jumptable 0000000000103EEC cases 4-7 ; +0x6c, 0x103ef0\nASR W23, W22, #4 ; +0x70, 0x103ef4\nBL sub_1047CC ; +0x74, 0x103ef8\nCBZ W23, loc_103FB8 ; +0x78, 0x103efc\nLDR Q0, [X21] ; +0x7c, 0x103f00\nBL sub_104774 ; +0x80, 0x103f04\nSTR Q0, [SP,#0xF0+var_C0] ; +0x84, 0x103f08\nLDR Q0, [X21,#0x10] ; +0x88, 0x103f0c\nSTR Q0, [SP,#0xF0+var_B0] ; +0x8c, 0x103f10\nLDR Q0, [X21,#0x20] ; +0x90, 0x103f14\nSTR Q0, [SP,#0xF0+var_A0] ; +0x94, 0x103f18\nLDR Q0, [X21,#0x30] ; +0x98, 0x103f1c\nSTR Q0, [SP,#0xF0+var_90] ; +0x9c, 0x103f20\nBL sub_103C94 ; +0xa0, 0x103f24\nLDP Q2, Q1, [SP,#0xF0+var_E0] ; +0xa4, 0x103f28\nLDR Q3, [SP,#0xF0+var_F0] ; +0xa8, 0x103f2c\nLDP Q7, Q16, [X29,#var_70] ; +0xac, 0x103f30\nLDP Q4, Q5, [SP,#0xF0+var_C0] ; +0xb0, 0x103f34\nSSHL V1.8H, V0.8H, V1.8H ; +0xb4, 0x103f38\nSSHL V2.8H, V0.8H, V2.8H ; +0xb8, 0x103f3c\nSSHL V3.8H, V0.8H, V3.8H ; +0xbc, 0x103f40\nAND V0.16B, V0.16B, V16.16B ; +0xc0, 0x103f44\nAND V1.16B, V16.16B, V1.16B ; +0xc4, 0x103f48\nAND V2.16B, V16.16B, V2.16B ; +0xc8, 0x103f4c\nAND V3.16B, V16.16B, V3.16B ; +0xcc, 0x103f50\nEXT V16.16B, V1.16B, V0.16B, #8 ; +0xd0, 0x103f54\nEXT V16.16B, V0.16B, V16.16B, #8 ; +0xd4, 0x103f58\nBL sub_1047F0 ; +0xd8, 0x103f5c\nLDP Q6, Q17, [SP,#0xF0+var_A0] ; +0xdc, 0x103f60\nUZP1 V3.4S, V16.4S, V1.4S ; +0xe0, 0x103f64\nUZP2 V1.4S, V16.4S, V1.4S ; +0xe4, 0x103f68\nUZP1 V16.4S, V0.4S, V2.4S ; +0xe8, 0x103f6c\nUZP2 V0.4S, V0.4S, V2.4S ; +0xec, 0x103f70\nUCVTF V2.4S, V3.4S ; +0xf0, 0x103f74\nUCVTF V3.4S, V16.4S ; +0xf4, 0x103f78\nLDR Q16, [SP,#0xF0+var_80] ; +0xf8, 0x103f7c\nFADD V4.4S, V4.4S, V7.4S ; +0xfc, 0x103f80\nFADD V5.4S, V5.4S, V7.4S ; +0x100, 0x103f84\nFADD V6.4S, V6.4S, V7.4S ; +0x104, 0x103f88\nFADD V7.4S, V17.4S, V7.4S ; +0x108, 0x103f8c\nUCVTF V1.4S, V1.4S ; +0x10c, 0x103f90\nUCVTF V0.4S, V0.4S ; +0x110, 0x103f94\nFMLA V6.4S, V2.4S, V16.4S ; +0x114, 0x103f98\nFMLA V7.4S, V1.4S, V16.4S ; +0x118, 0x103f9c\nFMLA V4.4S, V3.4S, V16.4S ; +0x11c, 0x103fa0\nFMLA V5.4S, V0.4S, V16.4S ; +0x120, 0x103fa4\nSTP Q6, Q7, [X21,#0x20] ; +0x124, 0x103fa8\nSTP Q4, Q5, [X21],#0x40 ; +0x128, 0x103fac\nSUB W23, W23, #1 ; +0x12c, 0x103fb0\nCBNZ W23, loc_103F00 ; +0x130, 0x103fb4\nMOV X23, XZR ; +0x134, 0x103fb8\nUBFX X22, X22, #2, #2 ; +0x138, 0x103fbc\nCMP W22, W23 ; +0x13c, 0x103fc0\nB.EQ def_103EEC; jumptable 0000000000103EEC default case ; +0x140, 0x103fc4\nBL sub_104774 ; +0x144, 0x103fc8\nBL sub_10430C ; +0x148, 0x103fcc\nLDUR Q2, [X29,#var_60] ; +0x14c, 0x103fd0\nLDR Q1, [X21,X23,LSL#4] ; +0x150, 0x103fd4\nBL sub_10479C ; +0x154, 0x103fd8\nSTR Q1, [X21,X23,LSL#4] ; +0x158, 0x103fdc\nADD X23, X23, #1 ; +0x15c, 0x103fe0\nB loc_103FC0 ; +0x160, 0x103fe4\nBL sub_104768 ; +0x164, 0x103fe8\nMOV X8, X21 ; +0x168, 0x103fec\nLDR Q1, [X8],#0x10 ; +0x16c, 0x103ff0\nLDUR Q2, [X29,#var_60] ; +0x170, 0x103ff4\nSUB W23, W23, #1 ; +0x174, 0x103ff8\nBL sub_10479C ; +0x178, 0x103ffc\nSTR Q1, [X21] ; +0x17c, 0x104000\nMOV X21, X8 ; +0x180, 0x104004\nCBNZ W23, loc_103FE8; jumptable 0000000000103EEC cases 0,1 ; +0x184, 0x104008\nB def_103EEC; jumptable 0000000000103EEC default case ; +0x188, 0x10400c\nNEG W8, W8; jumptable 0000000000103EEC cases 2,3 ; +0x18c, 0x104010\nASR W23, W22, #3 ; +0x190, 0x104014\nDUP V0.8H, W8 ; +0x194, 0x104018\nSTR Q0, [SP,#0xF0+var_B0] ; +0x198, 0x10401c\nCBZ W23, loc_104094 ; +0x19c, 0x104020\nLDR Q0, [X21] ; +0x1a0, 0x104024\nMOV X0, X20 ; +0x1a4, 0x104028\nMOV X1, X19 ; +0x1a8, 0x10402c\nSTR Q0, [SP,#0xF0+var_A0] ; +0x1ac, 0x104030\nLDR Q0, [X21,#0x10] ; +0x1b0, 0x104034\nSTR Q0, [SP,#0xF0+var_90] ; +0x1b4, 0x104038\nBL sub_103C94 ; +0x1b8, 0x10403c\nLDR Q1, [SP,#0xF0+var_B0] ; +0x1bc, 0x104040\nLDP Q4, Q3, [X29,#var_70] ; +0x1c0, 0x104044\nLDR Q5, [SP,#0xF0+var_80] ; +0x1c4, 0x104048\nSUB W23, W23, #1 ; +0x1c8, 0x10404c\nSSHL V1.8H, V0.8H, V1.8H ; +0x1cc, 0x104050\nAND V0.16B, V0.16B, V3.16B ; +0x1d0, 0x104054\nMOV V2.16B, V4.16B ; +0x1d4, 0x104058\nUCVTF V0.4S, V0.4S ; +0x1d8, 0x10405c\nAND V1.16B, V3.16B, V1.16B ; +0x1dc, 0x104060\nFMLA V2.4S, V0.4S, V5.4S ; +0x1e0, 0x104064\nMOV V0.16B, V4.16B ; +0x1e4, 0x104068\nUCVTF V1.4S, V1.4S ; +0x1e8, 0x10406c\nFMLA V0.4S, V1.4S, V5.4S ; +0x1ec, 0x104070\nZIP1 V1.4S, V2.4S, V0.4S ; +0x1f0, 0x104074\nZIP2 V0.4S, V2.4S, V0.4S ; +0x1f4, 0x104078\nLDR Q2, [SP,#0xF0+var_A0] ; +0x1f8, 0x10407c\nFADD V1.4S, V1.4S, V2.4S ; +0x1fc, 0x104080\nLDR Q2, [SP,#0xF0+var_90] ; +0x200, 0x104084\nFADD V0.4S, V0.4S, V2.4S ; +0x204, 0x104088\nSTP Q1, Q0, [X21],#0x20 ; +0x208, 0x10408c\nCBNZ W23, loc_104024 ; +0x20c, 0x104090\nMOV X23, XZR ; +0x210, 0x104094\nUBFX X22, X22, #2, #1 ; +0x214, 0x104098\nCMP W22, W23 ; +0x218, 0x10409c\nB.EQ def_103EEC; jumptable 0000000000103EEC default case ; +0x21c, 0x1040a0\nLDR Q0, [X21,X23,LSL#4] ; +0x220, 0x1040a4\nBL sub_104774 ; +0x224, 0x1040a8\nSTR Q0, [SP,#0xF0+var_90] ; +0x228, 0x1040ac\nBL sub_10430C ; +0x22c, 0x1040b0\nMOV X0, X20 ; +0x230, 0x1040b4\nMOV X1, X19 ; +0x234, 0x1040b8\nSTR Q0, [SP,#0xF0+var_A0] ; +0x238, 0x1040bc\nBL sub_10430C ; +0x23c, 0x1040c0\nLDP Q3, Q2, [X29,#var_70] ; +0x240, 0x1040c4\nLDR Q1, [SP,#0xF0+var_A0] ; +0x244, 0x1040c8\nLDR Q4, [SP,#0xF0+var_80] ; +0x248, 0x1040cc\nAND V0.16B, V0.16B, V2.16B ; +0x24c, 0x1040d0\nUCVTF V0.4S, V0.4S ; +0x250, 0x1040d4\nAND V1.16B, V1.16B, V2.16B ; +0x254, 0x1040d8\nMOV V2.16B, V3.16B ; +0x258, 0x1040dc\nFMLA V3.4S, V0.4S, V4.4S ; +0x25c, 0x1040e0\nLDR Q0, [SP,#0xF0+var_90] ; +0x260, 0x1040e4\nUCVTF V1.4S, V1.4S ; +0x264, 0x1040e8\nFMLA V2.4S, V1.4S, V4.4S ; +0x268, 0x1040ec\nINS V2.D[1], V3.D[0] ; +0x26c, 0x1040f0\nFADD V0.4S, V2.4S, V0.4S ; +0x270, 0x1040f4\nSTR Q0, [X21,X23,LSL#4] ; +0x274, 0x1040f8\nADD X23, X23, #1 ; +0x278, 0x1040fc\nB loc_10409C ; +0x27c, 0x104100\nNEG W9, W8; jumptable 0000000000103EEC case 8 ; +0x280, 0x104104\nDUP V0.8H, W9 ; +0x284, 0x104108\nNEG W9, W8,LSL#1 ; +0x288, 0x10410c\nSTR Q0, [SP,#0xF0+var_90] ; +0x28c, 0x104110\nDUP V0.8H, W9 ; +0x290, 0x104114\nSUB W9, W8, W8,LSL#2 ; +0x294, 0x104118\nSTR Q0, [SP,#0xF0+var_A0] ; +0x298, 0x10411c\nDUP V0.8H, W9 ; +0x29c, 0x104120\nNEG W9, W8,LSL#2 ; +0x2a0, 0x104124\nSTR Q0, [SP,#0xF0+var_B0] ; +0x2a4, 0x104128\nDUP V0.8H, W9 ; +0x2a8, 0x10412c\nADD W9, W8, W8,LSL#2 ; +0x2ac, 0x104130\nNEG W9, W9 ; +0x2b0, 0x104134\nSTR Q0, [SP,#0xF0+var_C0] ; +0x2b4, 0x104138\nDUP V0.8H, W9 ; +0x2b8, 0x10413c\nMOV W9, #0xFFFFFFFA ; +0x2bc, 0x104140\nMUL W9, W8, W9 ; +0x2c0, 0x104144\nSTR Q0, [SP,#0xF0+var_D0] ; +0x2c4, 0x104148\nSUB W8, W8, W8,LSL#3 ; +0x2c8, 0x10414c\nDUP V0.8H, W9 ; +0x2cc, 0x104150\nASR W22, W22, #5 ; +0x2d0, 0x104154\nBL sub_1047CC ; +0x2d4, 0x104158\nCBZ W22, loc_1042A0 ; +0x2d8, 0x10415c\nBL sub_104768 ; +0x2dc, 0x104160\nLDP Q2, Q1, [SP,#0xF0+var_A0] ; +0x2e0, 0x104164\nLDP Q4, Q3, [SP,#0xF0+var_C0] ; +0x2e4, 0x104168\nLDP Q6, Q5, [SP,#0xF0+var_E0] ; +0x2e8, 0x10416c\nLDR Q7, [SP,#0xF0+var_F0] ; +0x2ec, 0x104170\nLDP Q20, Q19, [X29,#var_70] ; +0x2f0, 0x104174\nSSHL V1.8H, V0.8H, V1.8H ; +0x2f4, 0x104178\nSSHL V2.8H, V0.8H, V2.8H ; +0x2f8, 0x10417c\nSSHL V3.8H, V0.8H, V3.8H ; +0x2fc, 0x104180\nSSHL V4.8H, V0.8H, V4.8H ; +0x300, 0x104184\nSSHL V5.8H, V0.8H, V5.8H ; +0x304, 0x104188\nSSHL V6.8H, V0.8H, V6.8H ; +0x308, 0x10418c\nSSHL V7.8H, V0.8H, V7.8H ; +0x30c, 0x104190\nAND V0.16B, V0.16B, V19.16B ; +0x310, 0x104194\nAND V1.16B, V19.16B, V1.16B ; +0x314, 0x104198\nAND V2.16B, V19.16B, V2.16B ; +0x318, 0x10419c\nAND V3.16B, V19.16B, V3.16B ; +0x31c, 0x1041a0\nAND V4.16B, V19.16B, V4.16B ; +0x320, 0x1041a4\nAND V5.16B, V19.16B, V5.16B ; +0x324, 0x1041a8\nAND V6.16B, V19.16B, V6.16B ; +0x328, 0x1041ac\nAND V7.16B, V19.16B, V7.16B ; +0x32c, 0x1041b0\nEXT V19.16B, V1.16B, V0.16B, #8 ; +0x330, 0x1041b4\nEXT V19.16B, V0.16B, V19.16B, #8 ; +0x334, 0x1041b8\nBL sub_1047F0 ; +0x338, 0x1041bc\nUZP1 V3.4S, V19.4S, V1.4S ; +0x33c, 0x1041c0\nUZP2 V1.4S, V19.4S, V1.4S ; +0x340, 0x1041c4\nEXT V19.16B, V5.16B, V4.16B, #8 ; +0x344, 0x1041c8\nEXT V19.16B, V4.16B, V19.16B, #8 ; +0x348, 0x1041cc\nINS V4.D[1], V5.D[0] ; +0x34c, 0x1041d0\nEXT V5.16B, V7.16B, V6.16B, #8 ; +0x350, 0x1041d4\nLDR Q21, [SP,#0xF0+var_80] ; +0x354, 0x1041d8\nEXT V5.16B, V6.16B, V5.16B, #8 ; +0x358, 0x1041dc\nINS V6.D[1], V7.D[0] ; +0x35c, 0x1041e0\nUZP1 V7.4S, V19.4S, V5.4S ; +0x360, 0x1041e4\nMOV V18.16B, V20.16B ; +0x364, 0x1041e8\nUZP2 V5.4S, V19.4S, V5.4S ; +0x368, 0x1041ec\nUZP1 V19.4S, V0.4S, V2.4S ; +0x36c, 0x1041f0\nUZP2 V0.4S, V0.4S, V2.4S ; +0x370, 0x1041f4\nUZP1 V2.4S, V4.4S, V6.4S ; +0x374, 0x1041f8\nUZP2 V4.4S, V4.4S, V6.4S ; +0x378, 0x1041fc\nMOV V6.16B, V20.16B ; +0x37c, 0x104200\nUCVTF V3.4S, V3.4S ; +0x380, 0x104204\nUCVTF V7.4S, V7.4S ; +0x384, 0x104208\nFMLA V18.4S, V3.4S, V21.4S ; +0x388, 0x10420c\nMOV V3.16B, V20.16B ; +0x38c, 0x104210\nFMLA V6.4S, V7.4S, V21.4S ; +0x390, 0x104214\nMOV V7.16B, V20.16B ; +0x394, 0x104218\nUCVTF V1.4S, V1.4S ; +0x398, 0x10421c\nUCVTF V5.4S, V5.4S ; +0x39c, 0x104220\nFMLA V3.4S, V1.4S, V21.4S ; +0x3a0, 0x104224\nFMLA V7.4S, V5.4S, V21.4S ; +0x3a4, 0x104228\nLDP Q1, Q5, [X21] ; +0x3a8, 0x10422c\nMOV V16.16B, V20.16B ; +0x3ac, 0x104230\nMOV V17.16B, V20.16B ; +0x3b0, 0x104234\nUCVTF V0.4S, V0.4S ; +0x3b4, 0x104238\nUCVTF V4.4S, V4.4S ; +0x3b8, 0x10423c\nFADD V1.4S, V1.4S, V20.4S ; +0x3bc, 0x104240\nFADD V5.4S, V5.4S, V20.4S ; +0x3c0, 0x104244\nUCVTF V19.4S, V19.4S ; +0x3c4, 0x104248\nUCVTF V2.4S, V2.4S ; +0x3c8, 0x10424c\nFMLA V16.4S, V0.4S, V21.4S ; +0x3cc, 0x104250\nFMLA V17.4S, V4.4S, V21.4S ; +0x3d0, 0x104254\nLDP Q0, Q4, [X21,#0x40] ; +0x3d4, 0x104258\nFMLA V1.4S, V19.4S, V21.4S ; +0x3d8, 0x10425c\nFMLA V5.4S, V2.4S, V21.4S ; +0x3dc, 0x104260\nLDP Q2, Q19, [X21,#0x60] ; +0x3e0, 0x104264\nFADD V4.4S, V6.4S, V4.4S ; +0x3e4, 0x104268\nFADD V0.4S, V18.4S, V0.4S ; +0x3e8, 0x10426c\nSTP Q1, Q5, [X21] ; +0x3ec, 0x104270\nFADD V2.4S, V3.4S, V2.4S ; +0x3f0, 0x104274\nFADD V3.4S, V7.4S, V19.4S ; +0x3f4, 0x104278\nLDP Q6, Q7, [X21,#0x20] ; +0x3f8, 0x10427c\nSTP Q0, Q4, [X21,#0x40] ; +0x3fc, 0x104280\nSTP Q2, Q3, [X21,#0x60] ; +0x400, 0x104284\nSUB W22, W22, #1 ; +0x404, 0x104288\nFADD V1.4S, V16.4S, V6.4S ; +0x408, 0x10428c\nFADD V5.4S, V17.4S, V7.4S ; +0x40c, 0x104290\nSTP Q1, Q5, [X21,#0x20] ; +0x410, 0x104294\nADD X21, X21, #0x80 ; +0x414, 0x104298\nCBNZ W22, loc_104160 ; +0x418, 0x10429c\nUBFX W22, W23, #1, #2 ; +0x41c, 0x1042a0\nCBZ W22, def_103EEC; jumptable 0000000000103EEC default case ; +0x420, 0x1042a4\nBL sub_1047B8 ; +0x424, 0x1042a8\nLDP Q1, Q0, [X29,#var_50] ; +0x428, 0x1042ac\nLDP Q3, Q4, [X29,#var_70] ; +0x42c, 0x1042b0\nLDR Q5, [SP,#0xF0+var_80] ; +0x430, 0x1042b4\nSUB W22, W22, #1 ; +0x434, 0x1042b8\nAND V0.16B, V0.16B, V4.16B ; +0x438, 0x1042bc\nAND V1.16B, V1.16B, V4.16B ; +0x43c, 0x1042c0\nMOV V2.16B, V3.16B ; +0x440, 0x1042c4\nSTP Q1, Q0, [X29,#var_50] ; +0x444, 0x1042c8\nUCVTF V0.4S, V0.4S ; +0x448, 0x1042cc\nFMLA V2.4S, V0.4S, V5.4S ; +0x44c, 0x1042d0\nLDP Q4, Q0, [X21] ; +0x450, 0x1042d4\nUCVTF V1.4S, V1.4S ; +0x454, 0x1042d8\nFMLA V3.4S, V1.4S, V5.4S ; +0x458, 0x1042dc\nFADD V1.4S, V2.4S, V4.4S ; +0x45c, 0x1042e0\nFADD V0.4S, V3.4S, V0.4S ; +0x460, 0x1042e4\nSTP Q1, Q0, [X21],#0x20 ; +0x464, 0x1042e8\nCBNZ W22, loc_1042A8 ; +0x468, 0x1042ec\nLDP X29, X30, [SP,#0xF0+var_s0]; jumptable 0000000000103EEC default case ; +0x46c, 0x1042f0\nLDP X20, X19, [SP,#0xF0+var_10] ; +0x470, 0x1042f4\nLDP X22, X21, [SP,#0xF0+var_20] ; +0x474, 0x1042f8\nLDR X23, [SP,#0xF0+var_30] ; +0x478, 0x1042fc\nMOV X0, XZR ; +0x47c, 0x104300\nADD SP, SP, #0x100 ; +0x480, 0x104304\nRET ; +0x484, 0x104308", "xrefs": [" @ 0x11f738"], "is_objc": false, "is_arm32": false, "is_arm64": false, "bida_info": "8.0.0 @ https://github.com/Stazzical/BromaIDA", "bindings_info": "commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings"}