{"type": "func", "start": 1068292, "end": 1070504, "name": "sub_104D04", "pseudocode": "// \n// sub_104D04 from 0x104d04 to 0x1055a8 (2212 bytes)\n// \n// 1 xrefs:\n// > sub_FCA14 @ 0xfcb1c\n// \n// This function is hookable on this platform!\n// \n// Using BromaIDA 8.0.0 @ https://github.com/Stazzical/BromaIDA\n// Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings\n// \n\nint8x16_t *__fastcall sub_104D04(\n __int64 a1,\n float *a2,\n float32x4_t *a3,\n _OWORD *a4,\n int a5,\n int a6,\n int a7,\n int a8,\n int a9,\n int a10,\n int a11)\n{\n int k; // w9\n int32x4_t v12; // t1\n int8x16_t v13; // q0\n int8x16_t v14; // q1\n __int64 v15; // x10\n __int64 m; // x9\n unsigned __int32 v17; // w12\n int v18; // w9\n float32x4_t *v19; // x11\n float32x4_t *n; // x10\n float32x4_t v21; // t1\n float32x4_t v22; // q0\n float32x4_t v23; // t1\n float32x4_t v24; // q2\n float32x4_t v25; // q3\n float32x4_t v26; // q4\n float32x4_t v27; // q5\n int8x16_t v28; // q0\n int8x16_t v29; // q1\n unsigned __int64 v30; // x15\n __int64 ii; // x9\n float *v32; // x13\n float v33; // s2\n int v34; // w14\n int32x4_t *v35; // x9\n float32x4_t *v36; // x11\n float32x4_t *v37; // x12\n int32x4_t *v38; // x13\n float32x4_t *jj; // x10\n int32x4_t v40; // t1\n int32x4_t v41; // q0\n int32x4_t v42; // t1\n float32x4_t v43; // q4\n float32x4_t v44; // q5\n float32x4_t v45; // q2\n float32x4_t v46; // q3\n int8x16_t v47; // q0\n int8x16_t v48; // q1\n float32x4_t v49; // q0\n int8x16_t v50; // q5\n int8x16_t v51; // q6\n __int64 v52; // x15\n __int64 v53; // x14\n float v54; // s2\n float32x4_t *v55; // x12\n int v56; // w11\n float *v57; // x9\n int8x16_t *kk; // x10\n float32x4_t v59; // t1\n int8x16_t v60; // q0\n int8x16_t v61; // q1\n __int64 mm; // x11\n float v63; // t1\n int i; // w11\n int32x4_t v65; // t1\n int32x4_t v66; // q0\n int32x4_t v67; // t1\n int8x16_t v68; // q2\n int8x16_t v69; // q3\n int v70; // w11\n unsigned __int32 v71; // t1\n unsigned __int32 v72; // t1\n unsigned __int64 v73; // x15\n __int64 v74; // x12\n float32x4_t v75; // q2\n float32x4_t v76; // q5\n int8x16_t v77; // q0\n int8x16_t v78; // q1\n int8x16_t v79; // q6\n int8x16_t v80; // q7\n int v81; // w16\n float *v82; // x10\n float *v83; // x11\n __int64 v84; // x12\n __int64 v85; // x13\n float *v86; // x14\n float *v87; // x15\n float v88; // t1\n float v89; // s0\n float v90; // t1\n float v91; // s1\n float v92; // t1\n float v93; // t1\n float v94; // s0\n float v95; // t1\n float v96; // s2\n float v97; // t1\n unsigned __int64 v98; // x16\n __int64 v99; // x17\n float32x4_t v100; // q4\n int8x16_t v101; // q3\n int8x16_t v102; // q5\n int8x16_t v103; // q2\n float32x4_t v104; // q3\n float32x4_t v105; // q2\n float32x4_t v106; // q4\n int8x16_t v107; // q5\n int8x16_t v108; // q6\n int v109; // w17\n float *v110; // x9\n float *v111; // x10\n float *v112; // x11\n float *v113; // x12\n float *v114; // x13\n float *v115; // x14\n float v116; // t1\n float v117; // s0\n float v118; // t1\n float v119; // s1\n float v120; // t1\n float v121; // t1\n float v122; // s0\n float v123; // t1\n float v124; // s2\n float v125; // t1\n __int64 v126; // x11\n int j; // w12\n int8x16_t v128; // q2\n int8x16_t v129; // q3\n __int64 v130; // x12\n int v131; // w8\n float *v132; // x9\n float *v133; // x10\n float v134; // s0\n float *v135; // x11\n __int64 v136; // x15\n __int64 v137; // x20\n __int64 v138; // x8\n __int64 v139; // x11\n int8x16_t *result; // x0\n float32x4_t *v141; // x1\n float32x4_t *v142; // x2\n int32x4_t *v143; // x3\n float32x4_t *v144; // x4\n __int64 v145; // x4\n __int64 v146; // x6\n float32x4_t *v147; // x1\n _OWORD *v148; // x2\n __int64 v149; // x3\n __int64 v150; // x5\n int v151; // w5\n int v152; // w21\n int v153; // w13\n float *v154; // x23\n __int64 v155; // x22\n __int64 v156; // x25\n float *v157; // x26\n __int64 v158; // x19\n float *nn; // x27\n unsigned int v160; // w16\n __int64 v161; // x29\n int v162; // w28\n int v163; // w30\n int8x16_t v164; // q1\n int8x16_t v165; // q3\n int32x4_t v166; // q4\n int32x4_t v167; // q2\n __int64 v168; // x28\n __int64 v169; // x16\n int v170; // w29\n __int128 v171; // q0\n float *v172; // x0\n int v173; // w17\n float *v174; // x30\n float *v175; // x12\n int v176; // w10\n __int64 v177; // x0\n __int64 v178; // x16\n int i1; // w21\n int v180; // w12\n int v181; // w21\n __int64 v182; // x4\n float *v183; // x20\n __int64 v184; // x10\n float *v185; // x22\n float *i2; // x23\n float32x4_t v187; // t1\n float32x4_t v188; // q0\n float32x4_t v189; // q1\n unsigned int v190; // w26\n unsigned int v191; // w27\n __int64 v192; // x29\n __int64 v193; // x30\n __int64 v194; // x16\n int v195; // w28\n int8x16_t v196; // q2\n int8x16_t v197; // q3\n int8x16_t v198; // q4\n int8x16_t v199; // q5\n int8x16_t v200; // q2\n int8x16_t v201; // q3\n int8x16_t v202; // q4\n int8x16_t v203; // q5\n int32x4_t v204; // q6\n int32x4_t v205; // q7\n __int64 v206; // x16\n __int64 v207; // x27\n float32x4_t *v208; // x26\n int v209; // w28\n int8x16_t v210; // q2\n float32x4_t v211; // q2\n int v212; // w9\n float v213; // t1\n float v214; // s0\n float v215; // s1\n __int64 v216; // x16\n __int64 v217; // x19\n int i3; // w20\n float v219; // s3\n int v220; // w9\n float *v221; // x20\n float *v222; // x19\n float *i4; // x21\n int32x4_t v224; // t1\n float32x4_t v225; // q0\n unsigned int v226; // w23\n unsigned int v227; // w24\n int8x16_t v228; // q1\n __int64 v229; // x26\n __int64 v230; // x27\n __int64 v231; // x28\n int v232; // w25\n int8x16_t v233; // q1\n int8x16_t v234; // q6\n int8x16_t v235; // q7\n int8x16_t v236; // q16\n int8x16_t v237; // q17\n int8x16_t v238; // q6\n int8x16_t v239; // q7\n int8x16_t v240; // q16\n int8x16_t v241; // q17\n int32x4_t v242; // q2\n int32x4_t v243; // q3\n __int64 v244; // x16\n __int64 v245; // x24\n float32x4_t *v246; // x23\n int v247; // w25\n int8x16_t v248; // q2\n float32x4_t v249; // q2\n int v250; // w9\n float v251; // t1\n float v252; // s0\n float v253; // s1\n __int64 v254; // x16\n __int64 v255; // x5\n int i5; // w7\n float v257; // s2\n int v258; // w17\n int v259; // w8\n float *v260; // x9\n float *i6; // x16\n unsigned int v262; // w3\n __int64 v263; // x7\n int v264; // w5\n int v265; // w19\n int8x16_t v266; // q1\n int8x16_t v267; // q2\n int8x16_t v268; // q0\n int8x16_t v269; // q3\n int32x4_t v270; // q4\n int32x4_t v271; // q2\n __int64 v272; // x5\n float32x4_t *v273; // x3\n int v274; // w7\n float *v275; // x12\n int v276; // w21\n float *v277; // x19\n float *v278; // x20\n float32x4_t v279; // q0\n int v280; // w8\n __int64 v281; // x9\n int i7; // w10\n float v283; // s0\n __int64 v284; // [xsp+0h] [xbp-80h]\n float32x2x2_t v285; // 0:kr00_16.16\n float32x2x2_t v286; // 0:kr10_16.16\n float32x2x2_t v287; // 0:kr20_16.16\n float32x2x2_t v288; // 0:kr30_16.16\n float32x2x2_t v289; // 0:kr40_16.16\n float32x2x2_t v290; // 0:kr50_16.16\n float32x2x2_t v291; // 0:d0.8,8:d1.8\n float32x2x2_t v292; // 0:d0.8,8:d1.8\n\n v137 = *(_QWORD *)(a1 + 8);\n v136 = *(_QWORD *)(a1 + 16);\n v138 = v136 + 4LL * a5;\n v139 = v137 + 4LL * a6;\n if ( a7 == 2 )\n {\n v145 = v138 + 2048;\n v146 = v139 + 4096;\n result = (int8x16_t *)a2;\n v147 = a3;\n v148 = a4;\n v149 = v138;\n v150 = v137 + 4LL * a6;\n for ( i = a8 >> 2; i; result += 2 )\n {\n v65 = *(int32x4_t *)(v149 - 16);\n v149 -= 16;\n v66 = v65;\n v67 = *(int32x4_t *)(v145 - 16);\n v145 -= 16;\n --i;\n v68 = vrev64q_s32(v66);\n v69 = vrev64q_s32(v67);\n v285.val[0].n64_u64[0] = vextq_s8(v68, v68, 8u).n128_u64[0];\n v285.val[1].n64_u64[0] = vextq_s8(v69, v69, 8u).n128_u64[0];\n vst2_f32((float *)result, v285);\n v286.val[0].n64_u64[0] = v68.n128_u64[0];\n v286.val[1].n64_u64[0] = v69.n128_u64[0];\n vst2_f32((float *)&result[1], v286);\n }\n v70 = a8 & 3;\n if ( (a8 & 3) != 0 )\n {\n do\n {\n v71 = *(_DWORD *)(v149 - 4);\n v149 -= 4;\n --v70;\n result->n128_u32[0] = v71;\n v72 = *(_DWORD *)(v145 - 4);\n v145 -= 4;\n result->n128_u32[1] = v72;\n result = (int8x16_t *)((char *)result + 8);\n }\n while ( v70 );\n }\n v73 = 0;\n v74 = -1;\n while ( (a9 >> 2) + (_DWORD)v74 != -1 )\n {\n v75 = v147[v74];\n v76 = (float32x4_t)v148[v73 / 0x10];\n v77 = vrev64q_s32(vmulq_f32(v75, *(float32x4_t *)(v149 + 16 * v74)));\n v78 = vrev64q_s32(vmulq_f32(v75, *(float32x4_t *)(v145 + 16 * v74)));\n v79 = vmlaq_f32(vextq_s8(v77, v77, 8u), *(float32x4_t *)(v150 + v73), v76);\n v80 = vmlaq_f32(vextq_s8(v78, v78, 8u), *(float32x4_t *)(v146 + v73), v76);\n v287.val[0].n64_u64[0] = v79.n128_u64[0];\n v287.val[1].n64_u64[0] = v80.n128_u64[0];\n vst2_f32((float *)result, v287);\n --v74;\n v288.val[0].n64_u64[0] = vextq_s8(v79, v79, 8u).n128_u64[0];\n v288.val[1].n64_u64[0] = vextq_s8(v80, v80, 8u).n128_u64[0];\n vst2_f32((float *)&result[1], v288);\n v73 += 16LL;\n result += 2;\n }\n v81 = a9 & 3;\n v82 = (float *)(v146 + v73);\n v83 = (float *)(v150 + v73);\n v84 = v145 - v73;\n v85 = v149 - v73;\n v86 = (float *)&v148[v73 / 0x10];\n v87 = (float *)&v147[v73 / 0xFFFFFFFFFFFFFFF0LL];\n if ( (a9 & 3) != 0 )\n {\n do\n {\n v88 = *(float *)(v85 - 4);\n v85 -= 4;\n v89 = v88;\n v90 = *--v87;\n v91 = v90;\n v92 = *v83++;\n --v81;\n result->n128_f32[0] = (float)(v89 * v91) + (float)(*v86 * v92);\n v93 = *(float *)(v84 - 4);\n v84 -= 4;\n v94 = v93;\n v95 = *v82++;\n v96 = v95;\n v97 = *v86++;\n result->n128_f32[1] = (float)(v94 * *v87) + (float)(v97 * v96);\n result = (int8x16_t *)((char *)result + 8);\n }\n while ( v81 );\n }\n v98 = 0;\n v99 = 0;\n while ( a10 >> 2 != (_DWORD)v99 )\n {\n v100 = *(float32x4_t *)&v86[4 * v99];\n v101 = vrev64q_s32(*(int32x4_t *)&v83[v98 / 4 - 4]);\n v102 = vrev64q_s32(*(int32x4_t *)&v82[v98 / 4 - 4]);\n v103 = vrev64q_s32(*(int32x4_t *)&v87[v98 / 4 - 4]);\n v104 = vmulq_f32(vextq_s8(v101, v101, 8u), v100);\n v105 = vextq_s8(v103, v103, 8u);\n v106 = vmulq_f32(vextq_s8(v102, v102, 8u), v100);\n v107 = vmlaq_f32(vnegq_f32(v104), *(float32x4_t *)(v85 + 16 * v99), v105);\n v108 = vmlaq_f32(vnegq_f32(v106), *(float32x4_t *)(v84 + 16 * v99), v105);\n v291.val[0].n64_u64[0] = vextq_s8(v107, v107, 8u).n128_u64[0];\n v289.val[0].n64_u64[0] = v107.n128_u64[0];\n v289.val[1].n64_u64[0] = v108.n128_u64[0];\n vst2_f32((float *)result, v289);\n v291.val[1].n64_u64[0] = vextq_s8(v108, v108, 8u).n128_u64[0];\n ++v99;\n vst2_f32((float *)&result[1], v291);\n v98 -= 16LL;\n result += 2;\n }\n v109 = a10 & 3;\n v110 = &v82[v98 / 4];\n v111 = &v83[v98 / 4];\n v112 = (float *)(v84 - v98);\n v113 = (float *)(v85 - v98);\n v114 = &v86[v98 / 0xFFFFFFFFFFFFFFFCLL];\n v115 = &v87[v98 / 4];\n if ( (a10 & 3) != 0 )\n {\n do\n {\n v116 = *--v115;\n v117 = v116;\n v118 = *--v111;\n v119 = v118;\n v120 = *v113++;\n --v109;\n result->n128_f32[0] = -(float)((float)(*v114 * v119) - (float)(v120 * v117));\n v121 = *--v110;\n v122 = v121;\n v123 = *v112++;\n v124 = v123;\n v125 = *v114++;\n result->n128_f32[1] = -(float)((float)(v125 * v122) - (float)(v124 * *v115));\n result = (int8x16_t *)((char *)result + 8);\n }\n while ( v109 );\n }\n v126 = 0;\n for ( j = a11 >> 2; j; result += 2 )\n {\n v128 = vrev64q_s32(vnegq_f32(*(float32x4_t *)&v111[v126 - 4]));\n v129 = vrev64q_s32(vnegq_f32(*(float32x4_t *)&v110[v126 - 4]));\n v292.val[0].n64_u64[0] = vextq_s8(v128, v128, 8u).n128_u64[0];\n v292.val[1].n64_u64[0] = vextq_s8(v129, v129, 8u).n128_u64[0];\n vst2_f32((float *)result, v292);\n --j;\n v290.val[0].n64_u64[0] = v128.n128_u64[0];\n v290.val[1].n64_u64[0] = v129.n128_u64[0];\n vst2_f32((float *)&result[1], v290);\n v126 -= 4;\n }\n v130 = 0;\n v131 = a11 & 3;\n v132 = &v110[v126];\n v133 = &v111[v126];\n if ( (a11 & 3) != 0 )\n {\n do\n {\n v134 = v133[v130 - 1];\n v135 = &v132[v130];\n --v131;\n --v130;\n result->n128_f32[0] = -v134;\n result->n128_f32[1] = -*(v135 - 1);\n result = (int8x16_t *)((char *)result + 8);\n }\n while ( v131 );\n }\n }\n else if ( a7 == 1 )\n {\n result = (int8x16_t *)a2;\n v141 = a3;\n v142 = (float32x4_t *)a4;\n v143 = (int32x4_t *)(v136 + 4LL * a5);\n v144 = (float32x4_t *)(v137 + 4LL * a6);\n for ( k = a8 >> 3; k; result += 2 )\n {\n v12 = v143[-2];\n v143 -= 2;\n --k;\n v13 = vrev64q_s32(v12);\n v14 = vrev64q_s32(v143[1]);\n *result = vextq_s8(v14, v14, 8u);\n result[1] = vextq_s8(v13, v13, 8u);\n }\n v15 = 0;\n for ( m = 0; (a8 & 7) != (_DWORD)m; ++m )\n {\n v17 = v143->n128_u32[--v15];\n result->n128_u32[m] = v17;\n }\n v18 = a9 >> 3;\n v19 = (int32x4_t *)((char *)v143 + v15 * 4);\n for ( n = (int8x16_t *)((char *)result - v15 * 4); v18; --v18 )\n {\n v21 = v141[-2];\n v141 -= 2;\n v22 = v21;\n v23 = v19[-2];\n v19 -= 2;\n v24 = *v144;\n v25 = v144[1];\n v144 += 2;\n v26 = *v142;\n v27 = v142[1];\n v142 += 2;\n v28 = vrev64q_s32(vmulq_f32(v22, v23));\n v29 = vrev64q_s32(vmulq_f32(v141[1], v19[1]));\n *n = vmlaq_f32(vextq_s8(v29, v29, 8u), v24, v26);\n n[1] = vmlaq_f32(vextq_s8(v28, v28, 8u), v25, v27);\n n += 2;\n }\n v30 = 0;\n for ( ii = 0; -(a9 & 7) != (_DWORD)ii; --ii )\n {\n v32 = (float *)v141 + ii;\n v33 = v19->n128_f32[ii - 1];\n n->n128_f32[v30 / 4] = (float)(v33 * *(v32 - 1)) + (float)(v142->n128_f32[v30 / 4] * v144->n128_f32[v30 / 4]);\n v30 += 4LL;\n }\n v34 = a10 >> 3;\n v35 = (float32x4_t *)((char *)v144 + v30);\n v36 = (float32x4_t *)((char *)v19 - v30);\n v37 = (float32x4_t *)((char *)v142 + v30);\n v38 = (float32x4_t *)((char *)v141 - v30);\n for ( jj = (float32x4_t *)((char *)n + v30); v34; --v34 )\n {\n v40 = v35[-2];\n v35 -= 2;\n v41 = v40;\n v42 = v38[-2];\n v38 -= 2;\n v43 = *v37;\n v44 = v37[1];\n v37 += 2;\n v45 = *v36;\n v46 = v36[1];\n v36 += 2;\n v47 = vrev64q_s32(v41);\n v48 = vrev64q_s32(v42);\n v49 = vnegq_f32(vmulq_f32(v44, vextq_s8(v47, v47, 8u)));\n v50 = vrev64q_s32(v38[1]);\n v51 = vrev64q_s32(v35[1]);\n *jj = vmlaq_f32(vnegq_f32(vmulq_f32(vextq_s8(v51, v51, 8u), v43)), v45, vextq_s8(v50, v50, 8u));\n jj[1] = vmlaq_f32(v49, v46, vextq_s8(v48, v48, 8u));\n jj += 2;\n }\n v52 = 0;\n v53 = 0;\n while ( -(a10 & 7) != (_DWORD)v52 )\n {\n result = (int32x4_t *)((char *)v38 + 4 * v52);\n v54 = v35->n128_f32[--v52];\n jj->n128_f32[v53] = -(float)((float)(v37->n128_f32[v53] * v54)\n - (float)(v36->n128_f32[v53] * result[-1].n128_f32[3]));\n ++v53;\n }\n v55 = (int32x4_t *)((char *)v35 - v53 * 4);\n v56 = a11 >> 3;\n v57 = (float *)((char *)v35 - v53 * 4 - 4);\n for ( kk = (float32x4_t *)((char *)jj + v53 * 4); v56; kk += 2 )\n {\n v59 = v55[-2];\n v55 -= 2;\n --v56;\n v57 -= 8;\n v60 = vrev64q_s32(vnegq_f32(v59));\n v61 = vrev64q_s32(vnegq_f32(v55[1]));\n *kk = vextq_s8(v61, v61, 8u);\n kk[1] = vextq_s8(v60, v60, 8u);\n }\n for ( mm = 0; (a11 & 7) != (_DWORD)mm; ++mm )\n {\n v63 = *v57--;\n kk->n128_f32[mm] = -v63;\n }\n }\n else\n {\n v284 = a6;\n v151 = 2 * a7;\n v152 = a8 >> 2;\n v153 = a7 >> 2;\n v154 = &a2[a7];\n v155 = 4 * a7;\n v156 = 4 * v155;\n v157 = &a2[2 * a7];\n v158 = v136 + 4LL * a5 - 16;\n for ( nn = &a2[3 * a7]; v152; v154 = (float *)((char *)v154 + v156) )\n {\n v160 = 0;\n v161 = 0;\n v162 = 0;\n v138 -= 16;\n v163 = 1536;\n while ( v153 != (_DWORD)v161 )\n {\n v164 = *(int8x16_t *)(v138 + 4LL * (unsigned int)(v163 - 1536));\n v165 = *(int8x16_t *)(v138 + 4LL * (v163 - 512));\n v166 = vextq_s8(v164, vextq_s8(*(int8x16_t *)(v138 + 4LL * (v163 - 1024)), v164, 8u), 8u);\n v164.n128_u64[1] = *(_QWORD *)(v138 + 4LL * (v163 - 1024));\n v167 = vextq_s8(v165, vextq_s8(*(int8x16_t *)(v138 + 4LL * v163), v165, 8u), 8u);\n v165.n128_u64[1] = *(_QWORD *)(v138 + 4LL * v163);\n v162 += 4;\n v163 += 2048;\n *(int32x4_t *)&a2[4 * v161] = vuzp2q_s32(v166, v167);\n *(int32x4_t *)&v154[4 * v161] = vuzp1q_s32(v166, v167);\n *(int32x4_t *)&v157[4 * v161] = vuzp2q_s32(v164, v165);\n *(int32x4_t *)&nn[4 * v161++] = vuzp1q_s32(v164, v165);\n v160 += 2048;\n }\n v168 = v162 & 0xFFFFFFFC;\n v169 = 4LL * v160;\n v170 = a7 & 3;\n if ( (a7 & 3) != 0 )\n {\n do\n {\n v171 = *(_OWORD *)(v158 + v169);\n v172 = &a2[v168];\n v173 = 3 * a7 + v168;\n v174 = &a2[a7 + (int)v168];\n v175 = &a2[v151 + (int)v168];\n --v170;\n ++v168;\n *v172 = *((float *)&v171 + 3);\n *v174 = *((float *)&v171 + 2);\n *v175 = *((float *)&v171 + 1);\n LODWORD(a2[v173]) = v171;\n v169 += 2048;\n }\n while ( v170 );\n }\n a2 = (float *)((char *)a2 + v156);\n --v152;\n v158 -= 16;\n nn = (float *)((char *)nn + v156);\n v157 = (float *)((char *)v157 + v156);\n }\n v176 = a8 & 3;\n v177 = v151;\n if ( (a8 & 3) != 0 )\n {\n do\n {\n v178 = 0;\n v138 -= 4;\n for ( i1 = a7; i1; ++a2 )\n {\n v180 = *(_DWORD *)(v138 + 4LL * ((unsigned int)v178 & 0xFFFFFE00));\n --i1;\n v178 += 512;\n *(_DWORD *)a2 = v180;\n }\n --v176;\n v158 -= 4;\n }\n while ( v176 );\n }\n v181 = a9 >> 2;\n v182 = v137 + 4 * v284 - 16;\n v183 = &a2[3 * a7];\n v184 = 4 * v155;\n v185 = &a2[v151];\n for ( i2 = &a2[a7]; v181; v158 -= 16 )\n {\n v187 = a3[-1];\n --a3;\n v188 = v187;\n v189 = *(float32x4_t *)a4;\n v190 = 0;\n v191 = 0;\n v192 = 0;\n v193 = 0;\n v194 = 0;\n v195 = 0;\n v138 -= 16;\n while ( v153 != (_DWORD)v192 )\n {\n v196 = vrev64q_s32(vmulq_f32(*(float32x4_t *)(v138 + 4LL * ((unsigned int)v193 & 0xFFFFF800)), v188));\n v197 = vrev64q_s32(vmulq_f32(*(float32x4_t *)(v138 + 4LL * (unsigned int)(v193 + 512)), v188));\n v198 = vrev64q_s32(vmulq_f32(*(float32x4_t *)(v138 + 4LL * (unsigned int)(v193 + 1024)), v188));\n v199 = vrev64q_s32(vmulq_f32(*(float32x4_t *)(v138 + 4LL * (unsigned int)(v193 + 1536)), v188));\n v200 = vmlaq_f32(\n vextq_s8(v196, v196, 8u),\n v189,\n *(float32x4_t *)(v139 + 4LL * ((unsigned int)v194 & 0xFFFFF000)));\n v201 = vmlaq_f32(vextq_s8(v197, v197, 8u), v189, *(float32x4_t *)(v139 + 4LL * (unsigned int)(v194 + 1024)));\n v202 = vmlaq_f32(vextq_s8(v198, v198, 8u), v189, *(float32x4_t *)(v139 + 4LL * (unsigned int)(v194 + 2048)));\n v203 = vmlaq_f32(vextq_s8(v199, v199, 8u), v189, *(float32x4_t *)(v139 + 4LL * (unsigned int)(v194 + 3072)));\n v204 = vextq_s8(v200, vextq_s8(v201, v200, 8u), 8u);\n v205 = vextq_s8(v202, vextq_s8(v203, v202, 8u), 8u);\n v200.n128_u64[1] = v201.n128_u64[0];\n v202.n128_u64[1] = v203.n128_u64[0];\n v195 += 4;\n v194 += 4096;\n v193 += 2048;\n v191 += 4096;\n *(int32x4_t *)&a2[4 * v192] = vuzp1q_s32(v200, v202);\n *(int32x4_t *)&i2[4 * v192] = vuzp2q_s32(v200, v202);\n *(int32x4_t *)&v185[4 * v192] = vuzp1q_s32(v204, v205);\n *(int32x4_t *)&v183[4 * v192++] = vuzp2q_s32(v204, v205);\n v190 += 2048;\n }\n v206 = v195 & 0xFFFFFFFC;\n v207 = 4LL * v191;\n v208 = (float32x4_t *)(v158 + 4LL * v190);\n v209 = a7 & 3;\n if ( (a7 & 3) != 0 )\n {\n do\n {\n v210 = vrev64q_s32(vmulq_f32(*v208, v188));\n v211 = vmlaq_f32(vextq_s8(v210, v210, 8u), v189, *(float32x4_t *)(v139 + v207));\n a2[v206] = v211.n128_f32[0];\n a2[a7 + (int)v206] = v211.n128_f32[1];\n a2[2 * a7 + (int)v206] = v211.n128_f32[2];\n --v209;\n v207 += 4096;\n a2[3 * a7 + (int)v206++] = v211.n128_f32[3];\n v208 += 128;\n }\n while ( v209 );\n }\n a2 = (float *)((char *)a2 + v184);\n v139 += 16;\n ++a4;\n --v181;\n v182 += 16;\n v183 = (float *)((char *)v183 + v184);\n v185 = (float *)((char *)v185 + v184);\n i2 = (float *)((char *)i2 + v184);\n }\n v212 = a9 & 3;\n if ( (a9 & 3) != 0 )\n {\n do\n {\n v213 = a3[-1].n128_f32[3];\n a3 = (float32x4_t *)((char *)a3 - 4);\n v214 = v213;\n v215 = *(float *)a4;\n v216 = 0;\n v217 = 0;\n v138 -= 4;\n for ( i3 = a7; i3; v216 += 512 )\n {\n v219 = *(float *)(v139 + 4LL * ((unsigned int)v217 & 0xFFFFFC00));\n --i3;\n v217 += 1024;\n *a2++ = (float)(*(float *)(v138 + 4LL * ((unsigned int)v216 & 0xFFFFFE00)) * v214) + (float)(v219 * v215);\n }\n v139 += 4;\n a4 = (_OWORD *)((char *)a4 + 4);\n --v212;\n v182 += 4;\n }\n while ( v212 );\n }\n v220 = a10 >> 2;\n v221 = &a2[v151];\n v222 = &a2[3 * a7];\n for ( i4 = &a2[a7]; v220; i4 = (float *)((char *)i4 + v184) )\n {\n v224 = a3[-1];\n --a3;\n v225 = *(float32x4_t *)a4;\n v226 = 0;\n v227 = 0;\n v228 = vrev64q_s32(v224);\n v229 = 0;\n v230 = 0;\n v231 = 0;\n v232 = 0;\n v139 -= 16;\n v233 = vextq_s8(v228, v228, 8u);\n while ( v153 != (_DWORD)v229 )\n {\n v234 = vrev64q_s32(*(int32x4_t *)(v139 + 4LL * ((unsigned int)v231 & 0xFFFFF000)));\n v235 = vrev64q_s32(*(int32x4_t *)(v139 + 4LL * (unsigned int)(v231 + 1024)));\n v236 = vrev64q_s32(*(int32x4_t *)(v139 + 4LL * (unsigned int)(v231 + 2048)));\n v237 = vrev64q_s32(*(int32x4_t *)(v139 + 4LL * (unsigned int)(v231 + 3072)));\n v238 = vmlaq_f32(\n vnegq_f32(vmulq_f32(vextq_s8(v234, v234, 8u), v225)),\n v233,\n *(float32x4_t *)(v138 + 4LL * ((unsigned int)v230 & 0xFFFFF800)));\n v239 = vmlaq_f32(\n vnegq_f32(vmulq_f32(vextq_s8(v235, v235, 8u), v225)),\n v233,\n *(float32x4_t *)(v138 + 4LL * (unsigned int)(v230 + 512)));\n v240 = vmlaq_f32(\n vnegq_f32(vmulq_f32(vextq_s8(v236, v236, 8u), v225)),\n v233,\n *(float32x4_t *)(v138 + 4LL * (unsigned int)(v230 + 1024)));\n v241 = vmlaq_f32(\n vnegq_f32(vmulq_f32(vextq_s8(v237, v237, 8u), v225)),\n v233,\n *(float32x4_t *)(v138 + 4LL * (unsigned int)(v230 + 1536)));\n v242 = vextq_s8(v238, vextq_s8(v239, v238, 8u), 8u);\n v243 = vextq_s8(v240, vextq_s8(v241, v240, 8u), 8u);\n v238.n128_u64[1] = v239.n128_u64[0];\n v240.n128_u64[1] = v241.n128_u64[0];\n v232 += 4;\n v231 += 4096;\n v230 += 2048;\n v227 += 4096;\n *(int32x4_t *)&a2[4 * v229] = vuzp1q_s32(v238, v240);\n *(int32x4_t *)&i4[4 * v229] = vuzp2q_s32(v238, v240);\n *(int32x4_t *)&v221[4 * v229] = vuzp1q_s32(v242, v243);\n *(int32x4_t *)&v222[4 * v229++] = vuzp2q_s32(v242, v243);\n v226 += 2048;\n }\n v244 = v232 & 0xFFFFFFFC;\n v245 = 4LL * v227;\n v246 = (float32x4_t *)(v138 + 4LL * v226);\n v247 = a7 & 3;\n if ( (a7 & 3) != 0 )\n {\n do\n {\n v248 = vrev64q_s32(*(int32x4_t *)(v182 + v245));\n v249 = vmlaq_f32(vnegq_f32(vmulq_f32(vextq_s8(v248, v248, 8u), v225)), v233, *v246);\n a2[v244] = v249.n128_f32[0];\n a2[a7 + (int)v244] = v249.n128_f32[1];\n a2[v151 + (int)v244] = v249.n128_f32[2];\n --v247;\n v245 += 4096;\n a2[3 * a7 + (int)v244++] = v249.n128_f32[3];\n v246 += 128;\n }\n while ( v247 );\n }\n a2 = (float *)((char *)a2 + v184);\n v138 += 16;\n ++a4;\n --v220;\n v182 -= 16;\n v222 = (float *)((char *)v222 + v184);\n v221 = (float *)((char *)v221 + v184);\n }\n v250 = a10 & 3;\n if ( (a10 & 3) != 0 )\n {\n do\n {\n v251 = a3[-1].n128_f32[3];\n a3 = (float32x4_t *)((char *)a3 - 4);\n v252 = v251;\n v253 = *(float *)a4;\n v254 = 0;\n v255 = 0;\n v139 -= 4;\n for ( i5 = a7; i5; v254 += 512 )\n {\n v257 = *(float *)(v139 + 4LL * ((unsigned int)v255 & 0xFFFFFC00));\n --i5;\n v255 += 1024;\n *a2++ = -(float)((float)(v257 * v253)\n - (float)(*(float *)(v138 + 4LL * ((unsigned int)v254 & 0xFFFFFE00)) * v252));\n }\n v138 += 4;\n a4 = (_OWORD *)((char *)a4 + 4);\n --v250;\n v182 -= 4;\n }\n while ( v250 );\n }\n v258 = v177;\n v259 = a11 >> 2;\n result = (int8x16_t *)&a2[v177];\n v260 = &a2[3 * a7];\n for ( i6 = &a2[a7]; v259; v182 -= 16 )\n {\n v262 = 0;\n v263 = 0;\n v264 = 0;\n v139 -= 16;\n v265 = 3072;\n while ( v153 != (_DWORD)v263 )\n {\n v266 = vnegq_f32(*(float32x4_t *)(v139 + 4LL * (unsigned int)(v265 - 3072)));\n v267 = vnegq_f32(*(float32x4_t *)(v139 + 4LL * (v265 - 2048)));\n v268 = vnegq_f32(*(float32x4_t *)(v139 + 4LL * v265));\n v269 = vnegq_f32(*(float32x4_t *)(v139 + 4LL * (v265 - 1024)));\n v270 = vextq_s8(v266, vextq_s8(v267, v266, 8u), 8u);\n v266.n128_u64[1] = v267.n128_u64[0];\n v271 = vextq_s8(v269, vextq_s8(v268, v269, 8u), 8u);\n v269.n128_u64[1] = v268.n128_u64[0];\n v264 += 4;\n v265 += 4096;\n *(int32x4_t *)&a2[4 * v263] = vuzp2q_s32(v270, v271);\n *(int32x4_t *)&i6[4 * v263] = vuzp1q_s32(v270, v271);\n result[v263] = vuzp2q_s32(v266, v269);\n *(int32x4_t *)&v260[4 * v263++] = vuzp1q_s32(v266, v269);\n v262 += 4096;\n }\n v272 = v264 & 0xFFFFFFFC;\n v273 = (float32x4_t *)(v182 + 4LL * v262);\n v274 = a7 & 3;\n if ( (a7 & 3) != 0 )\n {\n do\n {\n v275 = &a2[v272];\n v276 = 3 * a7 + v272;\n v277 = &a2[a7 + (int)v272];\n v278 = &a2[v258 + (int)v272];\n v279 = vnegq_f32(*v273);\n --v274;\n ++v272;\n *v275 = v279.n128_f32[3];\n *v277 = v279.n128_f32[2];\n *v278 = v279.n128_f32[1];\n a2[v276] = v279.n128_f32[0];\n v273 += 256;\n }\n while ( v274 );\n }\n a2 = (float *)((char *)a2 + v184);\n --v259;\n v260 = (float *)((char *)v260 + v184);\n result = (int8x16_t *)((char *)result + v184);\n i6 = (float *)((char *)i6 + v184);\n }\n v280 = a11 & 3;\n if ( (a11 & 3) != 0 )\n {\n do\n {\n v281 = 0;\n v139 -= 4;\n for ( i7 = a7; i7; ++a2 )\n {\n v283 = *(float *)(v139 + 4LL * ((unsigned int)v281 & 0xFFFFFC00));\n --i7;\n v281 += 1024;\n *a2 = -v283;\n }\n --v280;\n }\n while ( v280 );\n }\n }\n return result;\n}", "assembly": "; \n; sub_104D04 from 0x104d04 to 0x1055a8 (2212 bytes)\n; \n; 1 xrefs:\n; > sub_FCA14 @ 0xfcb1c\n; \n; This function is hookable on this platform!\n; \n; Using BromaIDA 8.0.0 @ https:;github.com/Stazzical/BromaIDA\n; Using bindings at commit ba9f177b at Thu Jul 16 22:52:06 2026 from https:;github.com/geode-sdk/bindings\n; \n\nSUB SP, SP, #0x80 ; +0x0, 0x104d04\nSTP X28, X27, [SP,#0x80+var_60] ; +0x4, 0x104d08\nSTP X26, X25, [SP,#0x80+var_50] ; +0x8, 0x104d0c\nSTP X24, X23, [SP,#0x80+var_40] ; +0xc, 0x104d10\nSTP X22, X21, [SP,#0x80+var_30] ; +0x10, 0x104d14\nSTP X20, X19, [SP,#0x80+var_20] ; +0x14, 0x104d18\nSTP X29, X30, [SP,#0x80+var_10] ; +0x18, 0x104d1c\nLDP X20, X15, [X0,#8] ; +0x1c, 0x104d20\nMOV W10, W7 ; +0x20, 0x104d24\nLDR W12, [SP,#0x80+arg_10] ; +0x24, 0x104d28\nLDR W7, [SP,#0x80+arg_8] ; +0x28, 0x104d2c\nLDR W9, [SP,#0x80+arg_0] ; +0x2c, 0x104d30\nCMP W6, #2 ; +0x30, 0x104d34\nADD X8, X15, W4,SXTW#2 ; +0x34, 0x104d38\nADD X11, X20, W5,SXTW#2 ; +0x38, 0x104d3c\nB.EQ loc_104D8C ; +0x3c, 0x104d40\nCMP W6, #1 ; +0x40, 0x104d44\nB.NE loc_104DD8 ; +0x44, 0x104d48\nLDP X29, X30, [SP,#0x80+var_10] ; +0x48, 0x104d4c\nLDP X20, X19, [SP,#0x80+var_20] ; +0x4c, 0x104d50\nLDP X22, X21, [SP,#0x80+var_30] ; +0x50, 0x104d54\nLDP X24, X23, [SP,#0x80+var_40] ; +0x54, 0x104d58\nLDP X26, X25, [SP,#0x80+var_50] ; +0x58, 0x104d5c\nLDP X28, X27, [SP,#0x80+var_60] ; +0x5c, 0x104d60\nSTR W12, [SP,#0x80+arg_0] ; +0x60, 0x104d64\nMOV X0, X1 ; +0x64, 0x104d68\nMOV X1, X2 ; +0x68, 0x104d6c\nMOV X2, X3 ; +0x6c, 0x104d70\nMOV X3, X8 ; +0x70, 0x104d74\nMOV X4, X11 ; +0x74, 0x104d78\nMOV W5, W10 ; +0x78, 0x104d7c\nMOV W6, W9 ; +0x7c, 0x104d80\nADD SP, SP, #0x80 ; +0x80, 0x104d84\nB loc_104818 ; +0x84, 0x104d88\nLDP X29, X30, [SP,#0x80+var_10] ; +0x88, 0x104d8c\nLDP X20, X19, [SP,#0x80+var_20] ; +0x8c, 0x104d90\nLDP X22, X21, [SP,#0x80+var_30] ; +0x90, 0x104d94\nLDP X24, X23, [SP,#0x80+var_40] ; +0x94, 0x104d98\nLDP X26, X25, [SP,#0x80+var_50] ; +0x98, 0x104d9c\nLDP X28, X27, [SP,#0x80+var_60] ; +0x9c, 0x104da0\nADD X4, X8, #0x800 ; +0xa0, 0x104da4\nADD X6, X11, #1,LSL#12 ; +0xa4, 0x104da8\nSTR W12, [SP,#0x80+arg_10] ; +0xa8, 0x104dac\nSTR W7, [SP,#0x80+arg_8] ; +0xac, 0x104db0\nSTR W9, [SP,#0x80+arg_0] ; +0xb0, 0x104db4\nMOV X0, X1 ; +0xb4, 0x104db8\nMOV X1, X2 ; +0xb8, 0x104dbc\nMOV X2, X3 ; +0xbc, 0x104dc0\nMOV X3, X8 ; +0xc0, 0x104dc4\nMOV X5, X11 ; +0xc4, 0x104dc8\nMOV W7, W10 ; +0xc8, 0x104dcc\nADD SP, SP, #0x80 ; +0xcc, 0x104dd0\nB loc_104A3C ; +0xd0, 0x104dd4\nSTR W12, [SP,#0x80+var_74] ; +0xd4, 0x104dd8\nSXTW X12, W5 ; +0xd8, 0x104ddc\nSXTW X16, W4 ; +0xdc, 0x104de0\nSTR X12, [SP,#0x80+var_80] ; +0xe0, 0x104de4\nSXTW X12, W6 ; +0xe4, 0x104de8\nSBFIZ X0, X6, #1, #0x20 ; ' ' ; +0xe8, 0x104dec\nSTR X12, [SP,#0x80+var_68] ; +0xec, 0x104df0\nLSL W5, W6, #1 ; +0xf0, 0x104df4\nLSL W19, W6, #2 ; +0xf4, 0x104df8\nADD X12, X0, W6,SXTW ; +0xf8, 0x104dfc\nADD X15, X15, X16,LSL#2 ; +0xfc, 0x104e00\nASR W21, W10, #2 ; +0x100, 0x104e04\nASR W13, W6, #2 ; +0x104, 0x104e08\nAND W14, W6, #3 ; +0x108, 0x104e0c\nADD X23, X1, W6,SXTW#2 ; +0x10c, 0x104e10\nADD W24, W6, W6,LSL#1 ; +0x110, 0x104e14\nSXTW X4, W5 ; +0x114, 0x104e18\nSXTW X22, W19 ; +0x118, 0x104e1c\nSBFIZ X25, X19, #2, #0x20 ; ' ' ; +0x11c, 0x104e20\nADD X26, X1, W5,SXTW#2 ; +0x120, 0x104e24\nSUB X19, X15, #0x10 ; +0x124, 0x104e28\nADD X27, X1, X12,LSL#2 ; +0x128, 0x104e2c\nMOV W15, W6 ; +0x12c, 0x104e30\nSTR X12, [SP,#0x80+var_70] ; +0x130, 0x104e34\nCBZ W21, loc_104F3C ; +0x134, 0x104e38\nMOV W16, WZR ; +0x138, 0x104e3c\nMOV X29, XZR ; +0x13c, 0x104e40\nMOV X28, XZR ; +0x140, 0x104e44\nSUB X8, X8, #0x10 ; +0x144, 0x104e48\nMOV W30, #0x600 ; +0x148, 0x104e4c\nCMP W13, W29 ; +0x14c, 0x104e50\nB.EQ loc_104ED0 ; +0x150, 0x104e54\nSBFIZ X0, X30, #2, #0x20 ; ' ' ; +0x154, 0x104e58\nLDR Q0, [X8,X0] ; +0x158, 0x104e5c\nSUB W0, W30, #0x600 ; +0x15c, 0x104e60\nLSL X0, X0, #2 ; +0x160, 0x104e64\nLDR Q1, [X8,X0] ; +0x164, 0x104e68\nSUB W0, W30, #0x400 ; +0x168, 0x104e6c\nSBFIZ X0, X0, #2, #0x20 ; ' ' ; +0x16c, 0x104e70\nLDR Q2, [X8,X0] ; +0x170, 0x104e74\nSUB W0, W30, #0x200 ; +0x174, 0x104e78\nSBFIZ X0, X0, #2, #0x20 ; ' ' ; +0x178, 0x104e7c\nLDR Q3, [X8,X0] ; +0x17c, 0x104e80\nEXT V4.16B, V2.16B, V1.16B, #8 ; +0x180, 0x104e84\nEXT V4.16B, V1.16B, V4.16B, #8 ; +0x184, 0x104e88\nINS V1.D[1], V2.D[0] ; +0x188, 0x104e8c\nEXT V2.16B, V0.16B, V3.16B, #8 ; +0x18c, 0x104e90\nEXT V2.16B, V3.16B, V2.16B, #8 ; +0x190, 0x104e94\nINS V3.D[1], V0.D[0] ; +0x194, 0x104e98\nUZP1 V0.4S, V4.4S, V2.4S ; +0x198, 0x104e9c\nUZP2 V2.4S, V4.4S, V2.4S ; +0x19c, 0x104ea0\nUZP1 V4.4S, V1.4S, V3.4S ; +0x1a0, 0x104ea4\nUZP2 V1.4S, V1.4S, V3.4S ; +0x1a4, 0x104ea8\nADD X28, X28, #4 ; +0x1a8, 0x104eac\nADD W30, W30, #0x800 ; +0x1ac, 0x104eb0\nSTR Q2, [X1,X29,LSL#4] ; +0x1b0, 0x104eb4\nSTR Q0, [X23,X29,LSL#4] ; +0x1b4, 0x104eb8\nSTR Q1, [X26,X29,LSL#4] ; +0x1b8, 0x104ebc\nSTR Q4, [X27,X29,LSL#4] ; +0x1bc, 0x104ec0\nADD X29, X29, #1 ; +0x1c0, 0x104ec4\nADD W16, W16, #0x800 ; +0x1c4, 0x104ec8\nB loc_104E50 ; +0x1c8, 0x104ecc\nMOV W16, W16 ; +0x1cc, 0x104ed0\nAND X28, X28, #0xFFFFFFFC ; +0x1d0, 0x104ed4\nLSL X16, X16, #2 ; +0x1d4, 0x104ed8\nMOV W29, W14 ; +0x1d8, 0x104edc\nCBZ W29, loc_104F20 ; +0x1dc, 0x104ee0\nLDR Q0, [X19,X16] ; +0x1e0, 0x104ee4\nADD W30, W15, W28 ; +0x1e4, 0x104ee8\nADD W12, W5, W28 ; +0x1e8, 0x104eec\nADD X0, X1, X28,LSL#2 ; +0x1ec, 0x104ef0\nADD W17, W24, W28 ; +0x1f0, 0x104ef4\nADD X30, X1, W30,SXTW#2 ; +0x1f4, 0x104ef8\nADD X12, X1, W12,SXTW#2 ; +0x1f8, 0x104efc\nSUB W29, W29, #1 ; +0x1fc, 0x104f00\nADD X28, X28, #1 ; +0x200, 0x104f04\nST1 {V0.S}[3], [X0] ; +0x204, 0x104f08\nST1 {V0.S}[2], [X30] ; +0x208, 0x104f0c\nST1 {V0.S}[1], [X12] ; +0x20c, 0x104f10\nSTR S0, [X1,W17,SXTW#2] ; +0x210, 0x104f14\nADD X16, X16, #0x800 ; +0x214, 0x104f18\nCBNZ W29, loc_104EE4 ; +0x218, 0x104f1c\nADD X1, X1, X25 ; +0x21c, 0x104f20\nSUB W21, W21, #1 ; +0x220, 0x104f24\nSUB X19, X19, #0x10 ; +0x224, 0x104f28\nADD X27, X27, X25 ; +0x228, 0x104f2c\nADD X26, X26, X25 ; +0x22c, 0x104f30\nADD X23, X23, X25 ; +0x230, 0x104f34\nCBNZ W21, loc_104E3C ; +0x234, 0x104f38\nAND W10, W10, #3 ; +0x238, 0x104f3c\nMOV X0, X4 ; +0x23c, 0x104f40\nCBZ W10, loc_104F7C ; +0x240, 0x104f44\nMOV X16, XZR ; +0x244, 0x104f48\nSUB X8, X8, #4 ; +0x248, 0x104f4c\nMOV W21, W6 ; +0x24c, 0x104f50\nCBZ W21, loc_104F70 ; +0x250, 0x104f54\nAND X12, X16, #0xFFFFFE00 ; +0x254, 0x104f58\nLDR W12, [X8,X12,LSL#2] ; +0x258, 0x104f5c\nSUB W21, W21, #1 ; +0x25c, 0x104f60\nADD X16, X16, #0x200 ; +0x260, 0x104f64\nSTR W12, [X1],#4 ; +0x264, 0x104f68\nCBNZ W21, loc_104F58 ; +0x268, 0x104f6c\nSUB W10, W10, #1 ; +0x26c, 0x104f70\nSUB X19, X19, #4 ; +0x270, 0x104f74\nCBNZ W10, loc_104F48 ; +0x274, 0x104f78\nLDR X10, [SP,#0x80+var_80] ; +0x278, 0x104f7c\nASR W21, W9, #2 ; +0x27c, 0x104f80\nADD W24, W6, W6,LSL#1 ; +0x280, 0x104f84\nAND X25, X0, #0xFFFFFFFF ; +0x284, 0x104f88\nADD X12, X20, X10,LSL#2 ; +0x288, 0x104f8c\nLDP X10, X16, [SP,#0x80+var_70] ; +0x28c, 0x104f90\nSUB X4, X12, #0x10 ; +0x290, 0x104f94\nADD X20, X1, X10,LSL#2 ; +0x294, 0x104f98\nLSL X10, X22, #2 ; +0x298, 0x104f9c\nADD X22, X1, X0,LSL#2 ; +0x29c, 0x104fa0\nADD X23, X1, X16,LSL#2 ; +0x2a0, 0x104fa4\nCBZ W21, loc_105160 ; +0x2a4, 0x104fa8\nLDR Q0, [X2,#-0x10]! ; +0x2a8, 0x104fac\nLDR Q1, [X3] ; +0x2ac, 0x104fb0\nMOV W26, WZR ; +0x2b0, 0x104fb4\nMOV W27, WZR ; +0x2b4, 0x104fb8\nMOV X29, XZR ; +0x2b8, 0x104fbc\nMOV X30, XZR ; +0x2bc, 0x104fc0\nMOV X16, XZR ; +0x2c0, 0x104fc4\nMOV X28, XZR ; +0x2c4, 0x104fc8\nSUB X8, X8, #0x10 ; +0x2c8, 0x104fcc\nCMP W13, W29 ; +0x2cc, 0x104fd0\nB.EQ loc_1050CC ; +0x2d0, 0x104fd4\nAND X12, X30, #0xFFFFF800 ; +0x2d4, 0x104fd8\nLSL X12, X12, #2 ; +0x2d8, 0x104fdc\nLDR Q2, [X8,X12] ; +0x2dc, 0x104fe0\nADD W12, W30, #0x200 ; +0x2e0, 0x104fe4\nLSL X12, X12, #2 ; +0x2e4, 0x104fe8\nLDR Q3, [X8,X12] ; +0x2e8, 0x104fec\nADD W12, W30, #0x400 ; +0x2ec, 0x104ff0\nLSL X12, X12, #2 ; +0x2f0, 0x104ff4\nLDR Q4, [X8,X12] ; +0x2f4, 0x104ff8\nADD W12, W30, #0x600 ; +0x2f8, 0x104ffc\nLSL X12, X12, #2 ; +0x2fc, 0x105000\nLDR Q5, [X8,X12] ; +0x300, 0x105004\nAND X12, X16, #0xFFFFF000 ; +0x304, 0x105008\nLSL X12, X12, #2 ; +0x308, 0x10500c\nLDR Q6, [X11,X12] ; +0x30c, 0x105010\nADD W12, W16, #0x400 ; +0x310, 0x105014\nLSL X12, X12, #2 ; +0x314, 0x105018\nLDR Q7, [X11,X12] ; +0x318, 0x10501c\nADD W12, W16, #0x800 ; +0x31c, 0x105020\nLSL X12, X12, #2 ; +0x320, 0x105024\nLDR Q16, [X11,X12] ; +0x324, 0x105028\nADD W12, W16, #0xC00 ; +0x328, 0x10502c\nLSL X12, X12, #2 ; +0x32c, 0x105030\nLDR Q17, [X11,X12] ; +0x330, 0x105034\nFMUL V2.4S, V2.4S, V0.4S ; +0x334, 0x105038\nFMUL V3.4S, V3.4S, V0.4S ; +0x338, 0x10503c\nFMUL V4.4S, V4.4S, V0.4S ; +0x33c, 0x105040\nFMUL V5.4S, V5.4S, V0.4S ; +0x340, 0x105044\nREV64 V2.4S, V2.4S ; +0x344, 0x105048\nREV64 V3.4S, V3.4S ; +0x348, 0x10504c\nREV64 V4.4S, V4.4S ; +0x34c, 0x105050\nREV64 V5.4S, V5.4S ; +0x350, 0x105054\nEXT V2.16B, V2.16B, V2.16B, #8 ; +0x354, 0x105058\nEXT V3.16B, V3.16B, V3.16B, #8 ; +0x358, 0x10505c\nEXT V4.16B, V4.16B, V4.16B, #8 ; +0x35c, 0x105060\nEXT V5.16B, V5.16B, V5.16B, #8 ; +0x360, 0x105064\nFMLA V2.4S, V1.4S, V6.4S ; +0x364, 0x105068\nFMLA V3.4S, V1.4S, V7.4S ; +0x368, 0x10506c\nFMLA V4.4S, V1.4S, V16.4S ; +0x36c, 0x105070\nFMLA V5.4S, V1.4S, V17.4S ; +0x370, 0x105074\nEXT V6.16B, V3.16B, V2.16B, #8 ; +0x374, 0x105078\nEXT V7.16B, V5.16B, V4.16B, #8 ; +0x378, 0x10507c\nEXT V6.16B, V2.16B, V6.16B, #8 ; +0x37c, 0x105080\nEXT V7.16B, V4.16B, V7.16B, #8 ; +0x380, 0x105084\nINS V2.D[1], V3.D[0] ; +0x384, 0x105088\nINS V4.D[1], V5.D[0] ; +0x388, 0x10508c\nUZP1 V3.4S, V6.4S, V7.4S ; +0x38c, 0x105090\nUZP2 V5.4S, V6.4S, V7.4S ; +0x390, 0x105094\nUZP1 V6.4S, V2.4S, V4.4S ; +0x394, 0x105098\nUZP2 V2.4S, V2.4S, V4.4S ; +0x398, 0x10509c\nADD X28, X28, #4 ; +0x39c, 0x1050a0\nADD X16, X16, #1,LSL#12 ; +0x3a0, 0x1050a4\nADD X30, X30, #0x800 ; +0x3a4, 0x1050a8\nADD W27, W27, #1,LSL#12 ; +0x3a8, 0x1050ac\nSTR Q6, [X1,X29,LSL#4] ; +0x3ac, 0x1050b0\nSTR Q2, [X23,X29,LSL#4] ; +0x3b0, 0x1050b4\nSTR Q3, [X22,X29,LSL#4] ; +0x3b4, 0x1050b8\nSTR Q5, [X20,X29,LSL#4] ; +0x3b8, 0x1050bc\nADD X29, X29, #1 ; +0x3bc, 0x1050c0\nADD W26, W26, #0x800 ; +0x3c0, 0x1050c4\nB loc_104FD0 ; +0x3c4, 0x1050c8\nMOV W12, W27 ; +0x3c8, 0x1050cc\nAND X16, X28, #0xFFFFFFFC ; +0x3cc, 0x1050d0\nLSL X27, X12, #2 ; +0x3d0, 0x1050d4\nADD X26, X19, W26,UXTW#2 ; +0x3d4, 0x1050d8\nMOV W28, W14 ; +0x3d8, 0x1050dc\nCBZ W28, loc_105138 ; +0x3dc, 0x1050e0\nLDR Q2, [X26] ; +0x3e0, 0x1050e4\nLDR Q3, [X11,X27] ; +0x3e4, 0x1050e8\nADD W12, W15, W16 ; +0x3e8, 0x1050ec\nADD X12, X1, W12,SXTW#2 ; +0x3ec, 0x1050f0\nFMUL V2.4S, V2.4S, V0.4S ; +0x3f0, 0x1050f4\nREV64 V2.4S, V2.4S ; +0x3f4, 0x1050f8\nEXT V2.16B, V2.16B, V2.16B, #8 ; +0x3f8, 0x1050fc\nFMLA V2.4S, V1.4S, V3.4S ; +0x3fc, 0x105100\nSTR S2, [X1,X16,LSL#2] ; +0x400, 0x105104\nST1 {V2.S}[1], [X12] ; +0x404, 0x105108\nADD W12, W25, W16 ; +0x408, 0x10510c\nADD X12, X1, W12,SXTW#2 ; +0x40c, 0x105110\nST1 {V2.S}[2], [X12] ; +0x410, 0x105114\nADD W12, W24, W16 ; +0x414, 0x105118\nADD X12, X1, W12,SXTW#2 ; +0x418, 0x10511c\nSUB W28, W28, #1 ; +0x41c, 0x105120\nADD X27, X27, #1,LSL#12 ; +0x420, 0x105124\nST1 {V2.S}[3], [X12] ; +0x424, 0x105128\nADD X16, X16, #1 ; +0x428, 0x10512c\nADD X26, X26, #0x800 ; +0x42c, 0x105130\nCBNZ W28, loc_1050E4 ; +0x430, 0x105134\nADD X1, X1, X10 ; +0x434, 0x105138\nADD X11, X11, #0x10 ; +0x438, 0x10513c\nADD X3, X3, #0x10 ; +0x43c, 0x105140\nSUB W21, W21, #1 ; +0x440, 0x105144\nADD X4, X4, #0x10 ; +0x444, 0x105148\nADD X20, X20, X10 ; +0x448, 0x10514c\nADD X22, X22, X10 ; +0x44c, 0x105150\nADD X23, X23, X10 ; +0x450, 0x105154\nSUB X19, X19, #0x10 ; +0x454, 0x105158\nCBNZ W21, loc_104FAC ; +0x458, 0x10515c\nAND W9, W9, #3 ; +0x45c, 0x105160\nCBZ W9, loc_1051C4 ; +0x460, 0x105164\nLDR S0, [X2,#-4]! ; +0x464, 0x105168\nLDR S1, [X3] ; +0x468, 0x10516c\nMOV X16, XZR ; +0x46c, 0x105170\nMOV X19, XZR ; +0x470, 0x105174\nSUB X8, X8, #4 ; +0x474, 0x105178\nMOV W20, W6 ; +0x478, 0x10517c\nCBZ W20, loc_1051B0 ; +0x47c, 0x105180\nAND X12, X16, #0xFFFFFE00 ; +0x480, 0x105184\nAND X17, X19, #0xFFFFFC00 ; +0x484, 0x105188\nLDR S2, [X8,X12,LSL#2] ; +0x488, 0x10518c\nLDR S3, [X11,X17,LSL#2] ; +0x48c, 0x105190\nSUB W20, W20, #1 ; +0x490, 0x105194\nADD X19, X19, #0x400 ; +0x494, 0x105198\nFMUL S2, S2, S0 ; +0x498, 0x10519c\nFMADD S2, S3, S1, S2 ; +0x49c, 0x1051a0\nSTR S2, [X1],#4 ; +0x4a0, 0x1051a4\nADD X16, X16, #0x200 ; +0x4a4, 0x1051a8\nCBNZ W20, loc_105184 ; +0x4a8, 0x1051ac\nADD X11, X11, #4 ; +0x4ac, 0x1051b0\nADD X3, X3, #4 ; +0x4b0, 0x1051b4\nSUB W9, W9, #1 ; +0x4b4, 0x1051b8\nADD X4, X4, #4 ; +0x4b8, 0x1051bc\nCBNZ W9, loc_105168 ; +0x4bc, 0x1051c0\nLDR X12, [SP,#0x80+var_70] ; +0x4c0, 0x1051c4\nASR W9, W7, #2 ; +0x4c4, 0x1051c8\nADD X20, X1, X0,LSL#2 ; +0x4c8, 0x1051cc\nADD W22, W6, W6,LSL#1 ; +0x4cc, 0x1051d0\nADD X19, X1, X12,LSL#2 ; +0x4d0, 0x1051d4\nLDR X12, [SP,#0x80+var_68] ; +0x4d4, 0x1051d8\nADD X21, X1, X12,LSL#2 ; +0x4d8, 0x1051dc\nCBZ W9, loc_1053B0 ; +0x4dc, 0x1051e0\nLDR Q1, [X2,#-0x10]! ; +0x4e0, 0x1051e4\nLDR Q0, [X3] ; +0x4e4, 0x1051e8\nMOV W23, WZR ; +0x4e8, 0x1051ec\nMOV W24, WZR ; +0x4ec, 0x1051f0\nREV64 V1.4S, V1.4S ; +0x4f0, 0x1051f4\nMOV X26, XZR ; +0x4f4, 0x1051f8\nMOV X27, XZR ; +0x4f8, 0x1051fc\nMOV X28, XZR ; +0x4fc, 0x105200\nMOV X25, XZR ; +0x500, 0x105204\nSUB X11, X11, #0x10 ; +0x504, 0x105208\nEXT V1.16B, V1.16B, V1.16B, #8 ; +0x508, 0x10520c\nCMP W13, W26 ; +0x50c, 0x105210\nB.EQ loc_10531C ; +0x510, 0x105214\nAND X12, X27, #0xFFFFF800 ; +0x514, 0x105218\nLSL X12, X12, #2 ; +0x518, 0x10521c\nLDR Q2, [X8,X12] ; +0x51c, 0x105220\nADD W12, W27, #0x200 ; +0x520, 0x105224\nLSL X12, X12, #2 ; +0x524, 0x105228\nLDR Q3, [X8,X12] ; +0x528, 0x10522c\nADD W12, W27, #0x400 ; +0x52c, 0x105230\nLSL X12, X12, #2 ; +0x530, 0x105234\nLDR Q4, [X8,X12] ; +0x534, 0x105238\nADD W12, W27, #0x600 ; +0x538, 0x10523c\nLSL X12, X12, #2 ; +0x53c, 0x105240\nLDR Q5, [X8,X12] ; +0x540, 0x105244\nAND X12, X28, #0xFFFFF000 ; +0x544, 0x105248\nLSL X12, X12, #2 ; +0x548, 0x10524c\nLDR Q6, [X11,X12] ; +0x54c, 0x105250\nADD W12, W28, #0x400 ; +0x550, 0x105254\nLSL X12, X12, #2 ; +0x554, 0x105258\nLDR Q7, [X11,X12] ; +0x558, 0x10525c\nADD W12, W28, #0x800 ; +0x55c, 0x105260\nLSL X12, X12, #2 ; +0x560, 0x105264\nLDR Q16, [X11,X12] ; +0x564, 0x105268\nADD W12, W28, #0xC00 ; +0x568, 0x10526c\nLSL X12, X12, #2 ; +0x56c, 0x105270\nLDR Q17, [X11,X12] ; +0x570, 0x105274\nREV64 V6.4S, V6.4S ; +0x574, 0x105278\nREV64 V7.4S, V7.4S ; +0x578, 0x10527c\nREV64 V16.4S, V16.4S ; +0x57c, 0x105280\nREV64 V17.4S, V17.4S ; +0x580, 0x105284\nEXT V6.16B, V6.16B, V6.16B, #8 ; +0x584, 0x105288\nEXT V7.16B, V7.16B, V7.16B, #8 ; +0x588, 0x10528c\nEXT V16.16B, V16.16B, V16.16B, #8 ; +0x58c, 0x105290\nEXT V17.16B, V17.16B, V17.16B, #8 ; +0x590, 0x105294\nFMUL V6.4S, V6.4S, V0.4S ; +0x594, 0x105298\nFMUL V7.4S, V7.4S, V0.4S ; +0x598, 0x10529c\nFMUL V16.4S, V16.4S, V0.4S ; +0x59c, 0x1052a0\nFMUL V17.4S, V17.4S, V0.4S ; +0x5a0, 0x1052a4\nFNEG V6.4S, V6.4S ; +0x5a4, 0x1052a8\nFNEG V7.4S, V7.4S ; +0x5a8, 0x1052ac\nFNEG V16.4S, V16.4S ; +0x5ac, 0x1052b0\nFNEG V17.4S, V17.4S ; +0x5b0, 0x1052b4\nFMLA V6.4S, V1.4S, V2.4S ; +0x5b4, 0x1052b8\nFMLA V7.4S, V1.4S, V3.4S ; +0x5b8, 0x1052bc\nFMLA V16.4S, V1.4S, V4.4S ; +0x5bc, 0x1052c0\nFMLA V17.4S, V1.4S, V5.4S ; +0x5c0, 0x1052c4\nEXT V2.16B, V7.16B, V6.16B, #8 ; +0x5c4, 0x1052c8\nEXT V3.16B, V17.16B, V16.16B, #8 ; +0x5c8, 0x1052cc\nEXT V2.16B, V6.16B, V2.16B, #8 ; +0x5cc, 0x1052d0\nEXT V3.16B, V16.16B, V3.16B, #8 ; +0x5d0, 0x1052d4\nINS V6.D[1], V7.D[0] ; +0x5d4, 0x1052d8\nINS V16.D[1], V17.D[0] ; +0x5d8, 0x1052dc\nUZP1 V4.4S, V2.4S, V3.4S ; +0x5dc, 0x1052e0\nUZP2 V2.4S, V2.4S, V3.4S ; +0x5e0, 0x1052e4\nUZP1 V3.4S, V6.4S, V16.4S ; +0x5e4, 0x1052e8\nUZP2 V5.4S, V6.4S, V16.4S ; +0x5e8, 0x1052ec\nADD X25, X25, #4 ; +0x5ec, 0x1052f0\nADD X28, X28, #1,LSL#12 ; +0x5f0, 0x1052f4\nADD X27, X27, #0x800 ; +0x5f4, 0x1052f8\nADD W24, W24, #1,LSL#12 ; +0x5f8, 0x1052fc\nSTR Q3, [X1,X26,LSL#4] ; +0x5fc, 0x105300\nSTR Q5, [X21,X26,LSL#4] ; +0x600, 0x105304\nSTR Q4, [X20,X26,LSL#4] ; +0x604, 0x105308\nSTR Q2, [X19,X26,LSL#4] ; +0x608, 0x10530c\nADD X26, X26, #1 ; +0x60c, 0x105310\nADD W23, W23, #0x800 ; +0x610, 0x105314\nB loc_105210 ; +0x614, 0x105318\nMOV W12, W24 ; +0x618, 0x10531c\nAND X16, X25, #0xFFFFFFFC ; +0x61c, 0x105320\nLSL X24, X12, #2 ; +0x620, 0x105324\nADD X23, X8, W23,UXTW#2 ; +0x624, 0x105328\nMOV W25, W14 ; +0x628, 0x10532c\nCBZ W25, loc_10538C ; +0x62c, 0x105330\nLDR Q2, [X4,X24] ; +0x630, 0x105334\nLDR Q3, [X23] ; +0x634, 0x105338\nADD W12, W15, W16 ; +0x638, 0x10533c\nADD X12, X1, W12,SXTW#2 ; +0x63c, 0x105340\nREV64 V2.4S, V2.4S ; +0x640, 0x105344\nEXT V2.16B, V2.16B, V2.16B, #8 ; +0x644, 0x105348\nFMUL V2.4S, V2.4S, V0.4S ; +0x648, 0x10534c\nFNEG V2.4S, V2.4S ; +0x64c, 0x105350\nFMLA V2.4S, V1.4S, V3.4S ; +0x650, 0x105354\nSTR S2, [X1,X16,LSL#2] ; +0x654, 0x105358\nST1 {V2.S}[1], [X12] ; +0x658, 0x10535c\nADD W12, W5, W16 ; +0x65c, 0x105360\nADD X12, X1, W12,SXTW#2 ; +0x660, 0x105364\nST1 {V2.S}[2], [X12] ; +0x664, 0x105368\nADD W12, W22, W16 ; +0x668, 0x10536c\nADD X12, X1, W12,SXTW#2 ; +0x66c, 0x105370\nSUB W25, W25, #1 ; +0x670, 0x105374\nADD X24, X24, #1,LSL#12 ; +0x674, 0x105378\nST1 {V2.S}[3], [X12] ; +0x678, 0x10537c\nADD X16, X16, #1 ; +0x67c, 0x105380\nADD X23, X23, #0x800 ; +0x680, 0x105384\nCBNZ W25, loc_105334 ; +0x684, 0x105388\nADD X1, X1, X10 ; +0x688, 0x10538c\nADD X8, X8, #0x10 ; +0x68c, 0x105390\nADD X3, X3, #0x10 ; +0x690, 0x105394\nSUB W9, W9, #1 ; +0x694, 0x105398\nSUB X4, X4, #0x10 ; +0x698, 0x10539c\nADD X19, X19, X10 ; +0x69c, 0x1053a0\nADD X20, X20, X10 ; +0x6a0, 0x1053a4\nADD X21, X21, X10 ; +0x6a4, 0x1053a8\nCBNZ W9, loc_1051E4 ; +0x6a8, 0x1053ac\nLDR W22, [SP,#0x80+var_74] ; +0x6ac, 0x1053b0\nAND W9, W7, #3 ; +0x6b0, 0x1053b4\nCBZ W9, loc_105418 ; +0x6b4, 0x1053b8\nLDR S0, [X2,#-4]! ; +0x6b8, 0x1053bc\nLDR S1, [X3] ; +0x6bc, 0x1053c0\nMOV X16, XZR ; +0x6c0, 0x1053c4\nMOV X5, XZR ; +0x6c4, 0x1053c8\nSUB X11, X11, #4 ; +0x6c8, 0x1053cc\nMOV W7, W6 ; +0x6cc, 0x1053d0\nCBZ W7, loc_105404 ; +0x6d0, 0x1053d4\nAND X17, X5, #0xFFFFFC00 ; +0x6d4, 0x1053d8\nAND X12, X16, #0xFFFFFE00 ; +0x6d8, 0x1053dc\nLDR S2, [X11,X17,LSL#2] ; +0x6dc, 0x1053e0\nLDR S3, [X8,X12,LSL#2] ; +0x6e0, 0x1053e4\nSUB W7, W7, #1 ; +0x6e4, 0x1053e8\nADD X5, X5, #0x400 ; +0x6e8, 0x1053ec\nFMUL S2, S2, S1 ; +0x6ec, 0x1053f0\nFNMSUB S2, S3, S0, S2 ; +0x6f0, 0x1053f4\nSTR S2, [X1],#4 ; +0x6f4, 0x1053f8\nADD X16, X16, #0x200 ; +0x6f8, 0x1053fc\nCBNZ W7, loc_1053D8 ; +0x6fc, 0x105400\nADD X8, X8, #4 ; +0x700, 0x105404\nADD X3, X3, #4 ; +0x704, 0x105408\nSUB W9, W9, #1 ; +0x708, 0x10540c\nSUB X4, X4, #4 ; +0x70c, 0x105410\nCBNZ W9, loc_1053BC ; +0x710, 0x105414\nLDP X9, X12, [SP,#0x80+var_70] ; +0x714, 0x105418\nMOV X17, X0 ; +0x718, 0x10541c\nASR W8, W22, #2 ; +0x71c, 0x105420\nADD X0, X1, X0,LSL#2 ; +0x720, 0x105424\nADD X9, X1, X9,LSL#2 ; +0x724, 0x105428\nADD X16, X1, X12,LSL#2 ; +0x728, 0x10542c\nADD W2, W6, W6,LSL#1 ; +0x72c, 0x105430\nAND X17, X17, #0xFFFFFFFF ; +0x730, 0x105434\nCBZ W8, loc_10554C ; +0x734, 0x105438\nMOV W3, WZR ; +0x738, 0x10543c\nMOV X7, XZR ; +0x73c, 0x105440\nMOV X5, XZR ; +0x740, 0x105444\nSUB X11, X11, #0x10 ; +0x744, 0x105448\nMOV W19, #0xC00 ; +0x748, 0x10544c\nCMP W13, W7 ; +0x74c, 0x105450\nB.EQ loc_1054E0 ; +0x750, 0x105454\nSBFIZ X12, X19, #2, #0x20 ; ' ' ; +0x754, 0x105458\nLDR Q0, [X11,X12] ; +0x758, 0x10545c\nSUB W12, W19, #0xC00 ; +0x75c, 0x105460\nLSL X12, X12, #2 ; +0x760, 0x105464\nLDR Q1, [X11,X12] ; +0x764, 0x105468\nSUB W12, W19, #0x800 ; +0x768, 0x10546c\nSBFIZ X12, X12, #2, #0x20 ; ' ' ; +0x76c, 0x105470\nLDR Q2, [X11,X12] ; +0x770, 0x105474\nSUB W12, W19, #0x400 ; +0x774, 0x105478\nSBFIZ X12, X12, #2, #0x20 ; ' ' ; +0x778, 0x10547c\nLDR Q3, [X11,X12] ; +0x77c, 0x105480\nFNEG V1.4S, V1.4S ; +0x780, 0x105484\nFNEG V2.4S, V2.4S ; +0x784, 0x105488\nFNEG V0.4S, V0.4S ; +0x788, 0x10548c\nFNEG V3.4S, V3.4S ; +0x78c, 0x105490\nEXT V4.16B, V2.16B, V1.16B, #8 ; +0x790, 0x105494\nEXT V4.16B, V1.16B, V4.16B, #8 ; +0x794, 0x105498\nINS V1.D[1], V2.D[0] ; +0x798, 0x10549c\nEXT V2.16B, V0.16B, V3.16B, #8 ; +0x79c, 0x1054a0\nEXT V2.16B, V3.16B, V2.16B, #8 ; +0x7a0, 0x1054a4\nINS V3.D[1], V0.D[0] ; +0x7a4, 0x1054a8\nUZP1 V0.4S, V4.4S, V2.4S ; +0x7a8, 0x1054ac\nUZP2 V2.4S, V4.4S, V2.4S ; +0x7ac, 0x1054b0\nUZP1 V4.4S, V1.4S, V3.4S ; +0x7b0, 0x1054b4\nUZP2 V1.4S, V1.4S, V3.4S ; +0x7b4, 0x1054b8\nADD X5, X5, #4 ; +0x7b8, 0x1054bc\nADD W19, W19, #1,LSL#12 ; +0x7bc, 0x1054c0\nSTR Q2, [X1,X7,LSL#4] ; +0x7c0, 0x1054c4\nSTR Q0, [X16,X7,LSL#4] ; +0x7c4, 0x1054c8\nSTR Q1, [X0,X7,LSL#4] ; +0x7c8, 0x1054cc\nSTR Q4, [X9,X7,LSL#4] ; +0x7cc, 0x1054d0\nADD X7, X7, #1 ; +0x7d0, 0x1054d4\nADD W3, W3, #1,LSL#12 ; +0x7d4, 0x1054d8\nB loc_105450 ; +0x7d8, 0x1054dc\nAND X5, X5, #0xFFFFFFFC ; +0x7dc, 0x1054e0\nADD X3, X4, W3,UXTW#2 ; +0x7e0, 0x1054e4\nMOV W7, W14 ; +0x7e4, 0x1054e8\nCBZ W7, loc_105530 ; +0x7e8, 0x1054ec\nLDR Q0, [X3] ; +0x7ec, 0x1054f0\nADD W19, W15, W5 ; +0x7f0, 0x1054f4\nADD W20, W17, W5 ; +0x7f4, 0x1054f8\nADD X12, X1, X5,LSL#2 ; +0x7f8, 0x1054fc\nADD W21, W2, W5 ; +0x7fc, 0x105500\nADD X19, X1, W19,SXTW#2 ; +0x800, 0x105504\nADD X20, X1, W20,SXTW#2 ; +0x804, 0x105508\nFNEG V0.4S, V0.4S ; +0x808, 0x10550c\nSUB W7, W7, #1 ; +0x80c, 0x105510\nADD X5, X5, #1 ; +0x810, 0x105514\nST1 {V0.S}[3], [X12] ; +0x814, 0x105518\nST1 {V0.S}[2], [X19] ; +0x818, 0x10551c\nST1 {V0.S}[1], [X20] ; +0x81c, 0x105520\nSTR S0, [X1,W21,SXTW#2] ; +0x820, 0x105524\nADD X3, X3, #1,LSL#12 ; +0x824, 0x105528\nCBNZ W7, loc_1054F0 ; +0x828, 0x10552c\nADD X1, X1, X10 ; +0x82c, 0x105530\nSUB W8, W8, #1 ; +0x830, 0x105534\nADD X9, X9, X10 ; +0x834, 0x105538\nADD X0, X0, X10 ; +0x838, 0x10553c\nADD X16, X16, X10 ; +0x83c, 0x105540\nSUB X4, X4, #0x10 ; +0x840, 0x105544\nCBNZ W8, loc_10543C ; +0x844, 0x105548\nAND W8, W22, #3 ; +0x848, 0x10554c\nCBZ W8, loc_105588 ; +0x84c, 0x105550\nMOV X9, XZR ; +0x850, 0x105554\nSUB X11, X11, #4 ; +0x854, 0x105558\nMOV W10, W6 ; +0x858, 0x10555c\nCBZ W10, loc_105580 ; +0x85c, 0x105560\nAND X12, X9, #0xFFFFFC00 ; +0x860, 0x105564\nLDR S0, [X11,X12,LSL#2] ; +0x864, 0x105568\nSUB W10, W10, #1 ; +0x868, 0x10556c\nADD X9, X9, #0x400 ; +0x86c, 0x105570\nFNEG S0, S0 ; +0x870, 0x105574\nSTR S0, [X1],#4 ; +0x874, 0x105578\nCBNZ W10, loc_105564 ; +0x878, 0x10557c\nSUB W8, W8, #1 ; +0x87c, 0x105580\nCBNZ W8, loc_105554 ; +0x880, 0x105584\nLDP X29, X30, [SP,#0x80+var_10] ; +0x884, 0x105588\nLDP X20, X19, [SP,#0x80+var_20] ; +0x888, 0x10558c\nLDP X22, X21, [SP,#0x80+var_30] ; +0x88c, 0x105590\nLDP X24, X23, [SP,#0x80+var_40] ; +0x890, 0x105594\nLDP X26, X25, [SP,#0x80+var_50] ; +0x894, 0x105598\nLDP X28, X27, [SP,#0x80+var_60] ; +0x898, 0x10559c\nADD SP, SP, #0x80 ; +0x89c, 0x1055a0\nRET ; +0x8a0, 0x1055a4", "xrefs": ["sub_FCA14 @ 0xfcb1c"], "is_objc": false, "is_arm32": false, "is_arm64": false, "bida_info": "8.0.0 @ https://github.com/Stazzical/BromaIDA", "bindings_info": "commit ba9f177b at Thu Jul 16 22:52:06 2026 from https://github.com/geode-sdk/bindings"}